PCF85132U/2DA/1,02 NXP Semiconductors, PCF85132U/2DA/1,02 Datasheet - Page 24

• Manufacturer Part Number: PCF85132U/2DA/1,02
• Description: IC LCD DISPLAY DRVR UNCASED
• Manufacturer: NXP Semiconductors

Specifications of PCF85132U/2DA/1,02

• Display Type: LCD
• Configuration: Multiple
• Interface: I²C
• Digits Or Characters: Any Digit Type
• Current - Supply: 60µA
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
PCF85132
Product data sheet
7.16.4 I
7.16.5 Input filters
7.16.6 I
The PCF85132 acts as an I
transmit data to an I
the acknowledge signals from the selected devices. Device selection depends on the
I
subaddress.
In single device applications, the hardware subaddress inputs A0 and A1 are normally tied
to V
A0 and A1 are tied to V
two devices with a common I
To enhance noise immunity in electrical adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
Two I
PCF85132.The entire I
Table 7.
The PCF85132 is a write-only device and will not respond to a read access, therefore bit 0
should always be logic 0. Bit 1 of the slave address byte, that a PCF85132 will respond to,
is defined by the level tied to its SA0 input (V
Having two reserved slave addresses allows the following on the same I
Bit
2
2
2
Fig 16. Acknowledgement on the I
C-bus slave address, on the transferred command data, and on the hardware
•
•
C-bus controller
C-bus protocol
SS
Up to 8 PCF85132 on the same I
The use of two types of LCD multiplex on the same I
2
C-bus slave addresses (0111 000 and 0111 001) are reserved for the
which defines the hardware subaddress 0. In multiple device applications
by transmitter
data output
by receiver
data output
SCL from
Slave address
7
MSB
0
I
2
master
C slave address byte
All information provided in this document is subject to legal disclaimers.
2
condition
6
1
C-bus master receiver. The only data output from the PCF85132 are
START
Rev. 1 — 23 November 2010
2
S
SS
C-bus slave address byte is shown in
or V
2
C-bus slave receiver. It does not initiate I
2
C-bus slave address have the same hardware subaddress.
DD
5
1
in accordance with a binary coding scheme such that no
1
2
C-bus
2
C-bus for very large LCD applications
4
1
SS
2
for logic 0 and V
3
0
LCD driver for low multiplex rates
2
C-bus
not acknowledge
2
0
acknowledge
Table
8
DD
for logic 1).
PCF85132
7.
acknowledgement
2
clock pulse for
1
SA0
C-bus transfers or
© NXP B.V. 2010. All rights reserved.
2
C-bus:
9
mbc602
0
LSB
R/W
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