XC3S1400AN-4FGG484I Xilinx Inc, XC3S1400AN-4FGG484I Datasheet - Page 87

• Manufacturer Part Number: XC3S1400AN-4FGG484I
• Description: IC FPGA SPARTAN-3AN 484FPGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3ANr

Specifications of XC3S1400AN-4FGG484I

• Number Of Logic Elements/cells: 25344
• Number Of Labs/clbs: 2816
• Total Ram Bits: 589824
• Number Of I /o: 372
• Number Of Gates: 1400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Optional Power-of-2 Addressing Mode
How to Determine the Current Addressing Mode
Spartan-3AN In-System Flash User Guide
UG333 (v2.1) January 15, 2009
R
As initially shipped, the Spartan
Default Addressing
Mode
page for potential file system control and error correction applications.
For some applications, however, a power-of-2 binary addressing method may prove more
natural. The ISF memory supports such an addressing mode, as highlighted in
page
Typically, this step is performed on a production tester and not by the FPGA application
itself.
Table A-1
Table A-1: Default Addressing Mode vs. Power-of-2 Addressing Mode
The
outlined in
application can read the
XC3S1400AN
Caution!
supports the Default Addressing Mode.
Caution!
In-System Flash memory (ISF) is programmed for this mode, it cannot be changed back to the
Default Addressing
Caution!
FPGA’s power supply must be cycled off and on before the change takes effect.
Caution!
such as FPGA configuration bitstreams, is corrupted once the ISF memory is irreversibly
changed over to the Power-of-2 addressing mode. The ISF memory must be erased and re-
written after changing to the optional power-of-2 addressing mode.
Page Size
XC3S200AN
XC3S400AN
XC3S700AN
XC3S50AN
89, but does require an additional irreversible programming step, described below.
provides 3% more total bits, providing additional “extra” bits and bytes within each
FPGA
illustrates how the addressing mode affects total memory size.
Table 6-6, page
The Power-of-2 Addressing Mode is not supported in simulation. Simulation only
Changing over to the power-of-2 addressing mode is irreversible. Once the FPGA’s
Immediately after
Any data stored while the FPGA ISF memory was in the
bit, bit 0, in the
Mode, highlighted in
Mode.
Total Bits by Addressing Mode
17,301,504
Status Register
1,081,344
4,325,376
8,650,752
Default
www.xilinx.com
66. If required, the ISF memory programmer or the FPGA
Status Register
Permanently Changing to the Power-of-2 Addressing
®
-3AN FPGA In-System Flash (ISF) memory uses the
by issuing a
Power-of-2
16,777,216
Table 2-2, page
1,048,576
4,194,304
8,388,608
indicates the current addressing mode, as
Status Register Read
Page Size by Addressing Mode
19. The
264 bytes
528 bytes
Default
Appendix A
Default Addressing
Default Addressing
command.
Power-of-2
256 bytes
512 bytes
Mode, the
Table A-3,
Mode,
87