XC3S1400AN-4FGG484I Xilinx Inc, XC3S1400AN-4FGG484I Datasheet - Page 47

• Manufacturer Part Number: XC3S1400AN-4FGG484I
• Description: IC FPGA SPARTAN-3AN 484FPGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3ANr

Specifications of XC3S1400AN-4FGG484I

• Number Of Logic Elements/cells: 25344
• Number Of Labs/clbs: 2816
• Total Ram Bits: 589824
• Number Of I /o: 372
• Number Of Gates: 1400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pre-initializing SRAM Page Buffer Contents
Spartan-3AN FPGA In-System Flash User Guide
UG333 (v2.1) January 15, 2009
R
•
•
The CSB signal must remain Low throughout the entire data transfer. A Low-to-High
transition starts the comparison between the addressed ISF memory page and the
designated SRAM page buffer. The operation is internally self-timed and completes in a
Page to Buffer Compare time, shown in
data
Table 4-8: Page to Buffer Compare Time, T
During the command execution time, the
indicates whether the Page to Buffer Compare operation is in progress or whether it has
completed.
When the operation completes, the Status Register bit 6, Compare, reflects the result of the
comparison.
The SRAM page buffers are not automatically pre-initialized to a known value before
executing a command. Consequently, never assume the contents of a buffer location.
Instead, the FPGA application must define each location.
The fastest way to pre-initialize a buffer is using the
any blank locations to 0xFF, which is the erased state of an ISF memory location.
Another easy method to pre-initialize a page buffer is to use an
command, pointed at a page that is known to be erased. This method copies the blank
page, which contains all 0xFF, into the page buffer. Although this method takes more time
to complete, about 400 μs, it has less overhead for the FPGA application.
Symbol
T
Similarly, serially clock in a 24-bit Page Address.
♦
♦
To end the command, drive CSB High on the falling edge of CLK.
COMP
sheet.
If using the default address scheme, see
If using power-of-2 addressing, see
Page to Buffer Compare Time
Description
www.xilinx.com
Table 4-8
READY/BUSY
Pre-initializing SRAM Page Buffer Contents
Table A-4, page 89
COMP
Table 2-2, page 19
FPGA
and specified in the
All
Buffer Write
bit (bit 7) of the
.
Page to Buffer Transfer
command. Ideally, define
Typ
—
.
Spartan-3AN FPGA
Max
Status Register
400
Units
μs
47