XC3S1400AN-4FGG484I Xilinx Inc, XC3S1400AN-4FGG484I Datasheet - Page 37

• Manufacturer Part Number: XC3S1400AN-4FGG484I
• Description: IC FPGA SPARTAN-3AN 484FPGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3ANr

Specifications of XC3S1400AN-4FGG484I

• Number Of Logic Elements/cells: 25344
• Number Of Labs/clbs: 2816
• Total Ram Bits: 589824
• Number Of I /o: 372
• Number Of Gates: 1400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Spartan-3AN FPGA In-System Flash User Guide
UG333 (v2.1) January 15, 2009
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The CSB signal must remain Low throughout the entire data transfer. If the transaction
reaches the end of a buffer, the ISF memory continues reading back at the beginning of the
buffer.
♦
♦
The slower version of the command
while the faster version
bits. At this point, the data supplied on the MOSI input does not matter.
On the next falling CLK edge, the requested data serially appears on the MISO output
port.
♦
♦
To end the data transfer, drive CSB High on the falling edge of CLK.
If using the default address scheme, see
If using power-of-2 addressing, see
Data is clocked out serially, most-significant bit first.
While CSB is Low, new data appears on the MISO output on every subsequent
falling CLK edge. The ISF memory automatically increments the implied address
counter through contiguous memory locations, as highlighted in
regardless of the address mode.
www.xilinx.com
(Table
3-6) of the command does require eight “don’t care”
(Table
Table A-3, page 89
3-7) does not require “don’t care” bits
Table 2-2, page 19
.
.
Figure
Buffer Read
3-5,
37