XC3S1400AN-4FGG484I Xilinx Inc, XC3S1400AN-4FGG484I Datasheet - Page 34

• Manufacturer Part Number: XC3S1400AN-4FGG484I
• Description: IC FPGA SPARTAN-3AN 484FPGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3ANr

Specifications of XC3S1400AN-4FGG484I

• Number Of Logic Elements/cells: 25344
• Number Of Labs/clbs: 2816
• Total Ram Bits: 589824
• Number Of I /o: 372
• Number Of Gates: 1400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 3: Read Commands
Table 3-4: Page to Buffer Transfer Command Summary
34
MOSI
Notes:
1. The Buffer 2 command is not available in the XC3S50AN because it has only one SRAM page buffer.
2. The Page to Buffer Transfer command is supported in simulation.
Pin
Page to Buffer 1
Page to Buffer 2
Transfer
Command
Transfer
Byte 1
0x53
0x55
(1)
•
•
The page transfer operation is internally self-timed and does not require CLK to toggle.
The page is transferred in 400 μs or less, specified as symbol T
FPGA data sheet
in the
application can monitor this bit to determine when the transfer is complete or the
application can wait 400 μs or more before accessing the data in the specified SRAM page
buffer.
Table 3-5: Page to Buffer Transfer, T
While the page transfer is in progress, the FPGA can access any other portion of the ISF
memory that is not actively involved in the transfer, including any of the following
commands.
•
•
•
Symbol
T
Similarly, serially clock in a 24-bit page address.
♦
♦
♦
To end the data transfer, deassert CSB High on the falling edge of CLK. Subsequently,
the entire contents of the addressed ISF memory page is transferred to the selected
SRAM page buffer.
Read from or write to the other SRAM page buffer, not involved in the present
operation.
♦
♦
Status Register Read
Information Read
XFER
Status Register
Default Addressing: See
Power-of-2 Addressing: See
Only the Page Address is required. Any byte address values are ignored.
If using the default address scheme, see
If using power-of-2 addressing, see
Buffer Read
Buffer Write
High Address
Page to Buffer Transfer Time
Byte 2
and shown in
is ‘0’ and returns to ‘1’ when the transfer completes. The FPGA
Description
ISF Page Address
www.xilinx.com
Table 5-3, page 53
Table
Table A-3, page 89
3-5. During the transfer, the
24-bit Page Address
XFER
Middle Address
Spartan-3AN FPGA In-System Flash User Guide
Table A-3, page 89
Byte 3
Table 2-2, page 19
FPGA
All
.
UG333 (v2.1) January 15, 2009
XFER
Typ
READY/BUSY
Byte Address Unused
—
.
in the
Low Address
Don’t Care
Byte 4
Spartan-3AN
Max
400
XX
bit (bit 7)
Units
μs
R