XC3S1400AN-4FGG484I Xilinx Inc, XC3S1400AN-4FGG484I Datasheet - Page 53

• Manufacturer Part Number: XC3S1400AN-4FGG484I
• Description: IC FPGA SPARTAN-3AN 484FPGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3ANr

Specifications of XC3S1400AN-4FGG484I

• Number Of Logic Elements/cells: 25344
• Number Of Labs/clbs: 2816
• Total Ram Bits: 589824
• Number Of I /o: 372
• Number Of Gates: 1400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Spartan-3AN FPGA In-System Flash User Guide
UG333 (v2.1) January 15, 2009
R
•
Table 5-2: Page Addressing Summary
Table 5-3: Page Address, Default Addressing Mode
A Low-to-High transition on the CSB input completes the command and the Flash then
erases the selected page. The erase operation is internally self-timed and completes in the
time shown in
time, the
operation is in progress or whether it has completed.
Table 5-4: Page Erase Time
3S1400AN
Bit Location
XC3S1400AN
3S200AN
3S400AN
3S700AN
XC3S200AN
XC3S400AN
XC3S700AN
3S50AN
XC3S50AN
Symbol
FPGA
♦
♦
Drive CSB High on the falling edge of CLK to end the command.
T
FPGA
PE
If using the default address scheme, see
If using power-of-2 addressing, see
READY/BUSY
23 22 21 20 19 18 17 16 15 14 13 12 11 10
23 22 21 20 19 18 17 16 15 14 13 12 11 10
0 0 0 0 0 0
0 0 0 0
0 0 0
0 0
Page Erase Time
Table 5-4
High Address
Pages
Total
2,048
4,096
4,096
512
Description
and specified in the
Page Address (4,096 pages)
bit (bit 7) of the
www.xilinx.com
Page Address (4,096 pages)
Page Size
Page Address (2,048 pages)
(Bytes)
264
528
Page Address (512 pages)
Default
Status Register
Every 512 bytes
Every 1K bytes
Middle Address
Table A-4, page 89
Alignment
Spartan-3AN FPGA data
XC3S1400AN
XC3S200AN
XC3S400AN
XC3S700AN
XC3S50AN
Table 5-3
Addressing Mode
FPGA
indicates whether the Page Erase
.
X X X X X X X X X X
9
9
Page Size
.
X X X X X X X X X
X X X X X X X X X
X X X X X X X X X
8
8
(Bytes)
256
512
Typ
7
7
13
15
Don’t Care bits
6
6
Don’t Care bits
Don’t Care bits
Don’t Care bits
Power-of-2
Low Address
sheet. During this
5
5
Every 256 bytes
Every 512 bytes
Max
4
4
32
35
Alignment
Page Erase
3
3
2
2
Units
ms
ms
1
1
0
0
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