XC3S1400AN-4FGG484I Xilinx Inc, XC3S1400AN-4FGG484I Datasheet - Page 54

• Manufacturer Part Number: XC3S1400AN-4FGG484I
• Description: IC FPGA SPARTAN-3AN 484FPGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3ANr

Specifications of XC3S1400AN-4FGG484I

• Number Of Logic Elements/cells: 25344
• Number Of Labs/clbs: 2816
• Total Ram Bits: 589824
• Number Of I /o: 372
• Number Of Gates: 1400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 5: Erase Commands
Block Erase
54
While the Page Erase operation is in progress, the FPGA can access any other portion of the
ISF memory, including any of the following commands.
•
•
•
The Block Erase command erases eight pages at one time, as shown in
proves useful when writing large amounts of data into the ISF memory. The Block Erase
command avoids using multiple Page Erase commands, resulting in a faster erase time for
between three to eight ISF pages.
To perform a Block Erase command, the FPGA application must perform the following
actions.
•
•
Read from or write to an SRAM page buffer, which are not used during an erase
operation.
♦
♦
Status Register Read
Information Read
Drive CSB Low while CLK is High or on the rising edge of CLK.
On the falling edge of CLK, serially clock in the appropriate Block Erase command
code, 0x50, most-significant bit first, as shown in
Buffer Read
Buffer Write
Block Erase
MOSI
MISO
CSB
CLK
A Block Erase command will not
erase a block of pages within a
sector that is protected by Sector
Protect or Sector Lockdown
SPI_ACCESS
(0x50)
www.xilinx.com
Figure 5-2: Block Erase Command
Spartan-3AN FPGA In-System Flash User Guide
Selected block of 8 pages is erased.
Other pages are unaffected.
READY/BUSY
Status Register
7
0 = Block Erase in progress
1 = Selected block of eight pages
Table
Flash Memory Array
is now erased
6
T
BE
5-5.
5
UG333 (v2.1) January 15, 2009
= 35 to 100 ms
Block address
4
3
UG332_c5_02_021207
Figure
2
1
5-2, which
0
R