XC3S1400AN-4FGG484I Xilinx Inc, XC3S1400AN-4FGG484I Datasheet - Page 12

• Manufacturer Part Number: XC3S1400AN-4FGG484I
• Description: IC FPGA SPARTAN-3AN 484FPGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3ANr

Specifications of XC3S1400AN-4FGG484I

• Number Of Logic Elements/cells: 25344
• Number Of Labs/clbs: 2816
• Total Ram Bits: 589824
• Number Of I /o: 372
• Number Of Gates: 1400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 1: Overview and SPI_ACCESS Interface
12
Example Detailed Command Sequence
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Figure 1-3
Register. This example shows the relation of the various control signals and the clock edges
when data appears and is captured.
The FPGA application selects the ISF memory by driving the SPI_ACCESS CSB input
Low when the CLK input is High and de-selects the ISF memory by driving the CSB
input High.
When CSB returns High, the current command is terminated.
The SPI Master, which is the FPGA application, starts every transaction by supplying
a command code or command sequence to the SPI_ACCESS MOSI input.
The CSB select input must be Low throughout the duration of a transaction. It cannot
change during the middle of an operation. Some ISF memory operations, such as
erasing a page or sector, continue automatically even after the SPI transaction is
complete.
The FPGA application supplies data to the ISF memory via the SPI_ACCESS MOSI
input, clocked on the falling edge of CLK.
The ISF memory captures any data supplied on the SPI_ACCESS MOSI input using
the rising edge of CLK.
The ISF memory presents data or status on the SPI_ACCESS MISO output using the
falling edge of CLK.
The FPGA application captures any data supplied by the ISF memory on the
SPI_ACCESS MISO output using the rising edge of CLK.
♦
All data, commands, and address information are supplied serially, ordered from
most-significant bit to least-significant bit.
When the CSB select input is High to deselect the ISF memory, the SPI_ACCESS MISO
output is High.
Because MISO output data changes every falling edge of CLK, the FPGA can also
capture data on the falling edge of CLK to simplify the FPGA application.
provides a detailed example of a command sequence that reads the
MOSI
MISO
CSB
CLK
Figure 1-3: Status Register Read Command Sequence
ISF Memory captures data on CLK rising edge
MSB
www.xilinx.com
0
1 1 0 1 0 1 1 1
Command Code (0xD7)
FPGA application captures data on CLK rising edge
1
CSB remains Low throughout entire transfer
2
3
4
5
Spartan-3AN FPGA In-System Flash User Guide
6
LSB
7
MSB
8
X X X
9 10 11 12 13 14 15 16
Status Byte
X
UG333 (v2.1) January 15, 2009
X
X
UG333_c1_03_022307
X
LSB
X
Status
R