LFXP3C-3TN144I Lattice, LFXP3C-3TN144I Datasheet - Page 9
LFXP3C-3TN144I
Manufacturer Part Number
LFXP3C-3TN144I
Description
FPGA - Field Programmable Gate Array 3.1K LUTs 100 I/O 1.8/2.5/3.3V IND
Manufacturer
Lattice
Specifications of LFXP3C-3TN144I
Number Of Programmable I/os
100
Data Ram Size
55296
Supply Voltage (max)
3.465 V
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.71 V
Package / Case
TQFP-144
Package
144TQFP
Family Name
LatticeXP
Device Logic Units
3000
Maximum Internal Frequency
320 MHz
Typical Operating Supply Voltage
1.8|2.5|3.3 V
Maximum Number Of User I/os
100
Ram Bits
55296
Re-programmability Support
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP3C-3TN144I
Manufacturer:
INTEL
Quantity:
1 143
Company:
Part Number:
LFXP3C-3TN144I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Board Timing Guidelines for the DDR SDRAM Controller IP Core
PCB Layout Recommendations for BGA Packages
Section III. LatticeXP Family Handbook Revision History
ispLEVER Controlled Place and Route.......................................................................................................... 17-10
Guided Map and PAR .................................................................................................................................... 17-14
Conclusion ..................................................................................................................................................... 17-15
Technical Support Assistance........................................................................................................................ 17-16
Introduction ...................................................................................................................................................... 18-1
Read Operation................................................................................................................................................ 18-2
Write Operation ................................................................................................................................................ 18-4
Address and Command Signals....................................................................................................................... 18-5
Board Design Guidelines ................................................................................................................................. 18-7
Technical Support Assistance.......................................................................................................................... 18-8
Appendix A. Example Extractions of Delays from Timing Reports .................................................................. 18-9
Introduction ...................................................................................................................................................... 19-1
BGA Breakout and Routing Examples ............................................................................................................. 19-1
PCB Fabrication Cost and Design Rule Considerations ................................................................................ 19-12
Advantages and Disadvantages of BGA Packaging ...................................................................................... 19-13
BGA Package Test and Assembly ................................................................................................................. 19-14
PCB Design Support ...................................................................................................................................... 19-17
Technical Support Assistance........................................................................................................................ 19-17
Revision History ............................................................................................................................................. 19-18
Revision History ............................................................................................................................................... 20-1
Running Multiple Routing Passes ......................................................................................................... 17-10
Using Multiple Placement Iterations (Cost Tables) ............................................................................... 17-11
Clock Boosting ...................................................................................................................................... 17-12
Notes on Guided Mapping .................................................................................................................... 17-15
Notes on Guided PAR........................................................................................................................... 17-15
Set-up Time Calculation for the Data Input (Max. Case) ........................................................................ 18-3
Hold Time Calculation for the Data Input (Min. Case)............................................................................. 18-3
Write Set-up ............................................................................................................................................ 18-4
Write Hold ............................................................................................................................................... 18-5
Set-up Calculation................................................................................................................................... 18-6
Hold Calculation ...................................................................................................................................... 18-7
64-ball csBGA BGA Breakout and Routing Example.............................................................................. 19-3
64-ball ucBGA BGA Breakout and Routing Example.............................................................................. 19-4
100-ball csBGA BGA Breakout and Routing Examples .......................................................................... 19-5
132-ball csBGA BGA Breakout Examples .............................................................................................. 19-7
144-ball csBGA BGA Breakout Examples .............................................................................................. 19-9
256-ball caBGA BGA Breakout Examples ............................................................................................ 19-11
8
LatticeXP Family Handbook
Table of Contents
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