LFXP3C-3TN144I Lattice, LFXP3C-3TN144I Datasheet - Page 324

• Manufacturer Part Number: LFXP3C-3TN144I
• Description: FPGA - Field Programmable Gate Array 3.1K LUTs 100 I/O 1.8/2.5/3.3V IND
• Manufacturer: Lattice

Specifications of LFXP3C-3TN144I

• Number Of Programmable I/os: 100
• Data Ram Size: 55296
• Supply Voltage (max): 3.465 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.71 V
• Package / Case: TQFP-144
• Package: 144TQFP
• Family Name: LatticeXP
• Device Logic Units: 3000
• Maximum Internal Frequency: 320 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 100
• Ram Bits: 55296
• Re-programmability Support: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Lattice ispTRACY Usage Guide
ispTRACY ispLA Program
After replacing the original design files with the ispTRACY Core Linker modified files, it is necessary to re-compile
®
the design and then program the device using the ispVM
software (see online documentation for running the
ispVM program). Once the device is successfully programmed, the ispLA program needs to be started. Figure 14-7
shows the ispLA launch button from the Project Navigator.
Figure 14-7. ispLA Launch Button in ispLEVER Project Navigator
ispLA provides for capture and display of data from the ispTRACY core. The program is used to setup the trigger
events counters, trigger location in data buffer, event patterns, event comparisons and data display. Figure 14-8
shows the initial startup windows required to run ispLA.
Figure 14-8. ispLA Program Window – New Project Setup
Once the project is set up, you can open up a trigger setup and viewing window for the project by clicking on
Window -> Show ispLA Window -> Device 0 -> Device 0 LA0. Figure 9 shows the ispLA window. There are three
tabs available under this window, trigger setup, event pattern and signal analysis (data view).
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