LFXP3C-3TN144I Lattice, LFXP3C-3TN144I Datasheet - Page 197

• Manufacturer Part Number: LFXP3C-3TN144I
• Description: FPGA - Field Programmable Gate Array 3.1K LUTs 100 I/O 1.8/2.5/3.3V IND
• Manufacturer: Lattice

Specifications of LFXP3C-3TN144I

• Number Of Programmable I/os: 100
• Data Ram Size: 55296
• Supply Voltage (max): 3.465 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.71 V
• Package / Case: TQFP-144
• Package: 144TQFP
• Family Name: LatticeXP
• Device Logic Units: 3000
• Maximum Internal Frequency: 320 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 100
• Ram Bits: 55296
• Re-programmability Support: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 9-34. FIFO Without Output Registers, End of Data Write Cycle
In this case, as seen above, the Almost Full flag is IN location 2 before the FIFO is filled. The Almost Full flag is
asserted when N-2 location is written, and Full flag is asserted when the last word is written into the FIFO.
Data_X data inputs do not get written as the FIFO is full (Full flag is high).
Now let us look at the waveforms when the contents of the FIFO are read out. Figure 9-35 shows the start of the
read cycle. RdEn goes high and the data read starts. The Full and Almost Full flags gets de-asserted as shown.
Almost Full
Almost
Reset
Empty
Empty
Clock
WrEn
RdEn
Data
Full
Q
Data_N-2
Data_N-1
9-32
Invalid Q
Data_N
LatticeECP/EC and LatticeXP Devices
Data_X
Data_X
Memory Usage Guide