LFXP3C-3TN144I Lattice, LFXP3C-3TN144I Datasheet - Page 206

• Manufacturer Part Number: LFXP3C-3TN144I
• Description: FPGA - Field Programmable Gate Array 3.1K LUTs 100 I/O 1.8/2.5/3.3V IND
• Manufacturer: Lattice

Specifications of LFXP3C-3TN144I

• Number Of Programmable I/os: 100
• Data Ram Size: 55296
• Supply Voltage (max): 3.465 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.71 V
• Package / Case: TQFP-144
• Package: 144TQFP
• Family Name: LatticeXP
• Device Logic Units: 3000
• Maximum Internal Frequency: 320 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 100
• Ram Bits: 55296
• Re-programmability Support: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figures 9-42 to 9-45 show the behavior of non-pipelined FIFO_DC or FIFO_DC without output registers. When we
pipeline the registers, the output data is delayed by one clock cycle. There is an extra option for output registers to
be enabled by the RdEn signal.
Figures 9-46 to 9-49 show similar waveforms for the FIFO_DC with output register and without output register
enable with RdEn. It should be noted that flags are asserted and de-asserted with similar timing to the FIFO_DC
without output registers. However it is only the data out ‘Q’ that is delayed by one clock cycle.
Figure 9-46. FIFO_DC With Output Registers, Start of Data Write Cycle
RPReset
WrClock
RdClock
Almost
Almost
Empty
Empty
Reset
WrEn
RdEn
Data
Full
Full
Q
Invalid Data
Data_1
Data_2
9-41
Invalid Q
Data_3
LatticeECP/EC and LatticeXP Devices
Data_4
Data_5
Memory Usage Guide