LFXP3C-3TN144I Lattice, LFXP3C-3TN144I Datasheet - Page 221

• Manufacturer Part Number: LFXP3C-3TN144I
• Description: FPGA - Field Programmable Gate Array 3.1K LUTs 100 I/O 1.8/2.5/3.3V IND
• Manufacturer: Lattice

Specifications of LFXP3C-3TN144I

• Number Of Programmable I/os: 100
• Data Ram Size: 55296
• Supply Voltage (max): 3.465 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.71 V
• Package / Case: TQFP-144
• Package: 144TQFP
• Family Name: LatticeXP
• Device Logic Units: 3000
• Maximum Internal Frequency: 320 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 100
• Ram Bits: 55296
• Re-programmability Support: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 10-2. DQ-DQS During READ
Figure 10-3. DQ-DQS During WRITE
Implementing DDR Memory Interfaces with the LatticeECP/EC Devices
This section describes how to implement the read and write sections of a DDR memory interface. It also provides
details of the DQ and DQS grouping rules associated with the LatticeECP/EC and LatticeXP devices.
DQS Grouping
Each DQS group generally consists of at least 10 I/Os (1DQS, 8DQ and 1DM) to implement a complete 8-bit DDR
memory interface. In the LatticeECP/EC devices each DQS signal will span across 16 I/Os and in the LatticeXP
devices the DQS will span 14 I/Os. Any 10 of these 16 I/Os can be used to implement an 8-bit DDR memory inter-
face. In addition to the DQS grouping, the user must also assign one reference voltage VREF1 for a given I/O bank.
The tables below show the total number of DQS groups available per I/O bank for each device and package.
(at PIN)
(at PIN)
DQS
DQ
(at REG)
(at REG)
(at PIN)
(at PIN)
DQS
DQS
DQ
DQ
Preamble
REG and 90
DQS PIN to
Phase Shift
Degree
10-2
Postamble
LatticeECP/EC and LatticeXP
DDR Usage Guide