LFXP3C-3TN144I Lattice, LFXP3C-3TN144I Datasheet - Page 344
LFXP3C-3TN144I
Manufacturer Part Number
LFXP3C-3TN144I
Description
FPGA - Field Programmable Gate Array 3.1K LUTs 100 I/O 1.8/2.5/3.3V IND
Manufacturer
Lattice
Specifications of LFXP3C-3TN144I
Number Of Programmable I/os
100
Data Ram Size
55296
Supply Voltage (max)
3.465 V
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.71 V
Package / Case
TQFP-144
Package
144TQFP
Family Name
LatticeXP
Device Logic Units
3000
Maximum Internal Frequency
320 MHz
Typical Operating Supply Voltage
1.8|2.5|3.3 V
Maximum Number Of User I/os
100
Ram Bits
55296
Re-programmability Support
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP3C-3TN144I
Manufacturer:
INTEL
Quantity:
1 143
Company:
Part Number:
LFXP3C-3TN144I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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In the Synplicity
value to 1000 instead of using the default value of 100. This will guide the tool to allow high fanout signals without
replicating the logic. In the LeonardoSpectrum tool project GUI, under Technology => Advanced Settings, users
can set the Max Fanout to be any number instead of the default value “0”.
Use ispLEVER Project Navigator Results for Device Utilization and Performance
Many synthesis tools give usage reports at the end of a successful synthesis. These reports show the name and
the number of library elements used in the design. The data in these reports do not represent the actual implemen-
tation of the design in the final Place and Route tool because the EDIF netlist will be further optimized during Map-
ping and Place and Route to achieve the best results. It is strongly recommended to use the MAP report and the
PAR report in the ispLEVER Project Navigator tool to understand the actual resource utilization in the device.
Although the synthesis report also provides a performance summary, the timing information is based on estimated
logic delays only. The Place & Route TRACE Report in the ispLEVER Project Navigator gives accurate perfor-
mance analysis of the design by including actual logic and routing delays in the paths.
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
e-mail:
Internet:
+1-503-268-8001 (Outside North America)
techsupport@latticesemi.com
www.latticesemi.com
®
project GUI, under the Implementation Options => Devices tab, users can set the Fanout Guide
13-17
HDL Synthesis Coding Guidelines
for Lattice Semiconductor FPGAs
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