LFXP3C-3TN144I Lattice, LFXP3C-3TN144I Datasheet - Page 230

• Manufacturer Part Number: LFXP3C-3TN144I
• Description: FPGA - Field Programmable Gate Array 3.1K LUTs 100 I/O 1.8/2.5/3.3V IND
• Manufacturer: Lattice

Specifications of LFXP3C-3TN144I

• Number Of Programmable I/os: 100
• Data Ram Size: 55296
• Supply Voltage (max): 3.465 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.71 V
• Package / Case: TQFP-144
• Package: 144TQFP
• Family Name: LatticeXP
• Device Logic Units: 3000
• Maximum Internal Frequency: 320 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 100
• Ram Bits: 55296
• Re-programmability Support: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 10-12. READ Data Transfer When DDRCLKPOL=0
DDRCLKPOL= 0
IO REGISTERS
Notes -
CLK TO SYNC
(1) DDR memory sends DQ aligned to DQS strobe.
(2) The DQS Strobe is delayed by 90 degree using the dedicated DQS logic.
(3) DQ is now center aligned to DQS Strobe.
(4) PRMBDET is the Preamble detect signal generated using the DQSBUFB primitive. This is used to
(5) The first set of IO registers A and B, capture data on the positive edge and negative edge of DQS.
(6) IO register C transfers data so that both data are now aligned to negative edge of DQS.
(7) DDCLKPOL signal generated will determine if the CLK going into the synchronization registers need to
(8) The IO Synchronization registers capture data at on positive edge of the FPGA CLK.
DQS at PIN
DQS at IOL
FPGA CLK
PRMBDET
generate the DDRCLKPOL signal.
be inverted. In this case, the DDRCLKPOL=0 as the CLK is LOW at the 1
DATAIN_P
DATAIN_N
DQ at PIN
DQ at IOL
C
A
B
P0
P0
10-11
N0
N0
P0
P1
P1
N0
P0
N1
P1
N1
P0
N0
N1
P1
st
LatticeECP/EC and LatticeXP
rising edge of PRMBDET.
DDR Usage Guide