ASD5010L500INT Arctic Silicon Devices, ASD5010L500INT Datasheet - Page 23

• Manufacturer Part Number: ASD5010L500INT
• Description: ADC (A/D Converters) A-D Conv, Dig Gain Dual 8 bit 500MSPS
• Manufacturer: Arctic Silicon Devices

Specifications of ASD5010L500INT

• Number Of Converters: 2
• Number Of Adc Inputs: 4
• Conversion Rate: 500 MSPs
• Resolution: 8 bit
• Snr: 49.5 dB
• Voltage Reference: 1 V
• Supply Voltage (max): 2 V
• Supply Voltage (min): 1.7 V
• Maximum Power Dissipation: 295 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-48
• Input Voltage: 1.8 V
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Preliminary Product Specification
LVDS Output Configuration and Control
The ASD5010 uses an 8-bit serial LVDS output interface as shown in the Timing Diagrams section. The different
selection of number of channels uses the LVDS outputs as defined by table 14.
Maximum data output bit-rate for ASD5010L1000 is 1 Gb/s and for ASD5010L500 500Mb/s. The maximum sampling rate
for the different configurations is given by table 15. The sampling rate is set by the frequency of the input clock (F
frame-rate, i.e. the frequency of the FCLK signal on the LVDS outputs, depends on the selected mode and the sampling
frequency (F
If the ASD5010 device is used at a low sampling rate the register bit low_clk_freq has to be set to '1'. See table 17 for
when to use this register bit for the different modes of operation.
ASD5010
low_clk_freq
lvds_advance
lvds_delay
phase_ddr<1:0>
btc_mode
msb_first
Name
S
) as defined in table 26.
Low clock frequency used.
Advance LVDS data bits and frame
clock by one clock cycle
Delay LVDS data bits and frame clock
by one clock cycle
Controls the phase of the LCLK
output relative to data.
Binary two's complement format for
ADC output data.
Serialized ADC output data comes out
with MSB first.
Single channel
Dual channel, channel 1
Dual channel, channel 2
Quad channel, channel 1
Quad channel, channel 2
Quad channel, channel 3
Quad channel, channel 4
ASD5010L1000
ASD5010L500
Product
Table 15: Maximum sampling rate for different ASD5010 configurations
Mode of operation
Description
Channel set-up
Single channel
Quad channel
Dual channel
Single channel
Table 16: Output data frame rate
Table 14: Use of LVDS outputs
[MSPS]
1000
Straight offset binary
500
D1A, D1B, D2A, D2B, D3A, D3B, D4A, D4B
D1A, D1B, D2A, D2B
D3A, D3B, D4A, D4B
D1A, D1B
D2A, D2B
D3A, D3B
D4A, D4B
rev 2.0, 2010.11.08
90 degrees
Default
LSB first
Inactive
Inactive
Inactive
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Frame-rate (FCLK frequency)
D15 D14D13D12D11D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Dual channel
LVDS outputs used
[MSPS]
500
250
F
F
F
S
S
S
/ 8
/ 4
/ 2
Quad channel
[MSPS]
250
125
X X
X 0
0 X
X 0 0 0
X
0 0 0
0 0 0
X
Confidential
Address
S
0x53
0x42
0x46
Hex
). The