ASD5020L640INT Arctic Silicon Devices, ASD5020L640INT Datasheet
ASD5020L640INT
Specifications of ASD5020L640INT
Related parts for ASD5020L640INT
ASD5020L640INT Summary of contents
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Preliminary Product Specification ASD5020 High Speed Mode Multi-Mode 12-bit 640 MSPS / 8-bit 1000 MSPS Analog to Digital Converter Features 12-bit Modes ● Single Channel Mode: F ● Dual Channel Mode: F ● Quad Channel Mode: F ● SNR: 71 ...
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Preliminary Product Specification Table of Contents Blizzard Product family: Products and Relations..................................................................................................................3 Specifications........................................................................................................................................................................ 4 ASD5020 High Speed Mode........................................................................................................................................... 5 Digital and Switching Specifications...................................................................................................................................... 6 Absolute Maximum Ratings.................................................................................................................................................. 7 Pin Configuration and Description......................................................................................................................................... 8 Startup Initialization............................................................................................................................................................. 10 Serial Interface.................................................................................................................................................................... 10 Timing ...
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Preliminary Product Specification Blizzard Product family: Products and Relations ASD5020 is a part of the ASD Blizzard family of ADCs for Instrumentation applications, with two main modes: High Speed Mode (ASD5020HS): 12-bit up to 640MSPS • Precision Mode (ASD5020PM): 14-bit ...
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Preliminary Product Specification Specifications AVDD=DVDD=OVDD=1.8V 160 MSPS, Quad channel 12-bit High Speed Mode, 50% clock duty cycle, -1dBFS 70 MHz input signal, S 1x/0dB digital gain (fine and coarse), unless otherwise noted Parameter DC accuracy No missing codes ...
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Preliminary Product Specification ASD5020 High Speed Mode AVDD=DVDD=OVDD=1.8V, 50% clock duty cycle, -1dBFS 70 MHz input signal, Gain = 1X, 12-bit output, RSDS output data levels, unless otherwise noted Parameter Performance SNR Signal to Noise Ratio Single Channel Mode , ...
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Preliminary Product Specification Digital and Switching Specifications AVDD= DVDD=OVDD=1.8V, RSDS output data levels, unless otherwise noted Parameter Clock Inputs DC Duty Cycle Compliance V Differential input voltage swing CK,diff V Differential input voltage swing, sine wave clock input CK,sine V ...
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Preliminary Product Specification Absolute Maximum Ratings Applying voltages to the pins beyond those specified in Table 1 could cause permanent damage to the circuit. Pin AVDD DVDD OVDD AVSS / DVSS Analog inputs and outputs CLKx LVDS outputs Digital inputs ...
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Preliminary Product Specification Pin Configuration and Description AVDD 1 CSN 2 SDATA 3 4 SCLK RESETN DVDD 7 DVSS 8 9 DP1A DN1A 10 DP1B 11 DN1B 12 PIN NAME AVDD Analog power supply, 1.8V CSN Chip ...
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Preliminary Product Specification PIN NAME DP2B LVDS channel 2B, positive output DN2B LVDS channel 2B, negative output LCKP LVDS bit clock, positive output LCKN LVDS bit clock, negative output FCLKP LVDS frame clock (1X), positive output FCLKN LVDS frame clock ...
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Preliminary Product Specification Startup Initialization As part of the ASD5020 power-on sequence both a reset and a power down cycle have to be applied to ensure correct start-up initialization. Reset can be done in one of two ways ...
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Preliminary Product Specification Timing Diagrams N+31 Analog input Input clock T LVDS LCLK P LCLK N FCLK N FCLK P D10 D11 DxnA N-4 N-4 N-2 N-2 N-2 N-2 N-2 N-2 N-2 N-2 N-2 N-2 N-2 N-2 ...
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Preliminary Product Specification N+126 N+124 Analog input Input clock T LVDS LCLK P LCLK N FCLK N FCLK P D10 D11 Dx1A N-16 N-16 N-8 N-8 N-8 N-8 N-8 N-8 N-8 N-8 N-8 N-8 N-8 N-8 D10 ...
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Preliminary Product Specification Register Map Name Description rst * Self-clearing software reset. sleep4_ch<4:1> Channel-specific sleep mode for a Quad Channel setup. sleep2_ch<2:1> Channel-specific sleep mode for a Dual Channel setup. sleep1_ch1 Channel-specific sleep mode for a Single Channel setup. sleep ...
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Preliminary Product Specification Name Description in a Dual Channel setup. cgain1_ch1 <3:0> Programmable coarse gain channel Single Channel setup. jitter_ctrl<7:0> Clock jitter adjustment. precision_mode * Enable Quad Channel 14 bits precision mode. high_speed_mode * Enable high speed ...
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Preliminary Product Specification Register Description Software Reset Name Description rst Self-clearing software reset. Setting the rst register bit to '1', restores the default value of all the internal registers including the rst register bit itself. Modes of Operation Name Description ...
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Preliminary Product Specification Input Select Name Description inp_sel_adc1<4:0> Input select for adc 1. inp_sel_adc2<4:0> Input select for adc 2. inp_sel_adc3<4:0> Input select for adc 3. inp_sel_adc4<4:0> Input select for adc 4. Each ADC is connected to the four input signals ...
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Preliminary Product Specification Full-scale Control Name Description fs_cntrl<5:0> Fine adjust ADC full scale range The full-scale voltage range of ASD5020 can be adjusted using an internal 6-bit DAC controlled by the fs_cntrl register. Changing the value in the register by ...
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Preliminary Product Specification The ext_vcm_bc register controls the driving strength in the buffer supplying the voltage on the VCM pin. If this pin is not in use, the buffer can be switched off. If current is drawn from the VCM ...
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Preliminary Product Specification Start-up and Clock Jitter Control Name Description startup_ctrl<2:0> Controls start-up time. jitter_ctrl<7:0> Clock jitter adjustment. To optimize start up time, a register is provided where the start-up time in number of clock cycles can be set. Some ...
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Preliminary Product Specification jitter_ctrl<7:0> allows the user to set a trade-off between power consumption and clock jitter. If all bits in the register is set low, the clock signal is stopped. The clock jitter depends on the number of bits ...
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Preliminary Product Specification LVDS Output Configuration and Control Name Description lvds_output_mode Sets the number of LVDS output bits. <2:0> low_clk_freq Low clock frequency used. lvds_advance Advance LVDS data bits and frame clock by one clock cycle lvds_delay Delay LVDS data ...
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Preliminary Product Specification Table 16: Maximum sampling rate vs number of output bits for different ASD5020 configurations Number of bits Dual 8 Mode of operation High speed, single channel High speed, dual channel High speed, quad channel ...
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Preliminary Product Specification To ease timing in the receiver when using multiple ASD5020, the device has the option to adjust the timing of the output data and the frame clock. The propagation delay with respect to the ADC input clock ...
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Preliminary Product Specification LVDS Drive Strength Programmability Name Description ilvds_lclk<2:0> LVDS current drive programmability for LCLKP and LCLKN pins. ilvds_frame<2:0> LVDS current drive programmability for FCLKP and FCLKN pins. ilvds_dat<2:0> LVDS current drive programmability for output data pins. The current ...
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Preliminary Product Specification Table 20: LVDS output internal termination for LCLK, FCLK and data ASD5020 term_*<2:0> LVDS Internal Termination 000 Termination disabled 001 260 010 150 011 94 100 125 101 80 110 66 111 55 rev 2.0, 2010.11.08 Page ...
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Preliminary Product Specification Power Mode Control Name Description sleep4_ch<4:1> Channel-specific sleep mode for a Quad Channel setup. sleep2_ch<2:1> Channel-specific sleep mode for a Dual Channel setup. sleep1_ch1 Channel-specific sleep mode for a Single Channel setup. sleep Go to sleep-mode. pd ...
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Preliminary Product Specification Programmable Gain Name Description cgain_cfg Configures the coarse gain setting fine_gain_en Enable use of fine gain. cgain4_ch1 <3:0> Programmable coarse gain channel Quad Channel setup. cgain4_ch2 <3:0> Programmable coarse gain channel ...
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Preliminary Product Specification cgain_cfg There is a digital fine gain implemented for each ADC branch to adjust the fine gain errors between the branches. The gain is controlled by fgain_branch* as defined in table 23. For the high speed interleaved ...
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Preliminary Product Specification Analog Input Invert Name Description invert4_ch<4:1> Channel specific swapping of the analog input signal for a Quad Channel setup. invert2_ch<2:1> Channel specific swapping of the analog input signal for a Dual Channel setup. invert1_ch1 Channel specific swapping ...
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Preliminary Product Specification Theory of Operation ASD5020 is a multi Mode high-speed, CMOS ADC, consisting of 8 ADC branches, configured in different channel modes, using interleaving to achieve high speed sampling. For all practical purposes, the device can be considered ...
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Preliminary Product Specification side of the resistors may be used to provide dynamic charging currents and may improve performance. The resistors form a low pass filter with the capacitor, and values must therefore be determined by requirements for the application. ...
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Preliminary Product Specification all circuitry in the clock distribution utmost importance to avoid crosstalk between the ADC output bits and the clock and between the analog input signal and the clock since such crosstalk often results in ...
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Preliminary Product Specification Package Mechanical Data QFN48 Pin 1 ID (Top side Symbol Min A 0 5. 0.6 ASD5020 D D2 Pin 1 ID Radius ...
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... Product ASD5020 Preliminary Product Specification Ordering information Model Temp. range ASD5020L640INT -40 to +85 °C (1) MSL, Peak Temp: The moisture sensitivity level rating classified according to the JEDEC industry standard and to peak solder temperature. Datasheet status Objective Product Specification: The values and functionality describe design targets only. Specifications and functionality can be changed without notice Preliminary Product Specification: The specifications are based on initial design results ...