WM8985GEFL Wolfson Microelectronics, WM8985GEFL Datasheet - Page 94
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WM8985GEFL
Manufacturer Part Number
WM8985GEFL
Description
Audio CODECs Multimedia CODEC with Class D HP
Manufacturer
Wolfson Microelectronics
Datasheet
1.WM8985GEFL.pdf
(121 pages)
Specifications of WM8985GEFL
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
QFN-32
Minimum Operating Temperature
- 25 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
WM8985GEFL/R
Manufacturer:
TAIYO
Quantity:
4 023
Part Number:
WM8985GEFL/R
Manufacturer:
WOLFSON
Quantity:
20 000
WM8985
REGISTER BITS BY ADDRESS
Notes:
1. Default values of N/A indicate non-latched data bits (e.g. software reset or volume update bits).
2. Register bits marked as “Reserved” should not be changed from the default.
w
0 (00h)
1 (01h)
2 (02h)
REGISTER
ADDRESS
[8:0]
8
7
6
5
4
3
2
1:0
8
7
6
5
4
3
2
BIT
RESET
OUT4MIXEN
OUT3MIXEN
PLLEN
MICBEN
BIASEN
BUFIOEN
VMIDSEL[1:0]
ROUT1EN
LOUT1EN
SLEEP
BOOSTENR
BOOSTENL
INPPGAENR
INPPGAENL
LABEL
N/A
0
0
0
0
0
0
0
00
0
0
0
0
0
0
0
DEFAULT
Software reset
Reserved. Initialise to 0
OUT4 mixer enable
0=disabled
1=enabled
OUT3 mixer enable
0=disabled
1=enabled
PLL enable
0=PLL off
1=PLL on
Microphone Bias Enable
0 = OFF (high impedance output)
1 = ON
Analogue amplifier bias control
0=disabled
1=enabled
Unused input/output tie off buffer enable
0=disabled
1=enabled
Reference string impedance to VMID pin
00 = off (250k Ω VMID to AGND1)
01=75k Ω
10=300k Ω
11=5k Ω
ROUT1 output enable
0=disabled
1=enabled
LOUT1 output enable
0=disabled
1=enabled
0 = normal device operation
1 = residual current reduced in device standby
mode
Right channel Input BOOST enable
0 = Boost stage OFF
1 = Boost stage ON
Left channel Input BOOST enable
0 = Boost stage OFF
1 = Boost stage ON
Right channel input PGA enable
0 = disabled
1 = enabled
Left channel input PGA enable
0 = disabled
1 = enabled
DESCRIPTION
PD, Rev 4.6, July 2009
Resetting the
Chip
Power
Management
Power
Management
Master Clock
and Phase
Locked Loop
(PLL)
Input Signal
Path
Power
Management
Power
Management
Power
Management
Power
Management
Power
Management
Power
Management
Power
Management
Power
Management
Power
Management
Power
Management
Production Data
REFER TO
94