WM8985GEFL Wolfson Microelectronics, WM8985GEFL Datasheet - Page 81

• Manufacturer Part Number: WM8985GEFL
• Description: Audio CODECs Multimedia CODEC with Class D HP
• Manufacturer: Wolfson Microelectronics

Specifications of WM8985GEFL

• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-32
• Minimum Operating Temperature: - 25 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Production Data
AUDIO SAMPLE RATES
MASTER CLOCK AND PHASE LOCKED LOOP (PLL)
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Table 45 Sample Rate Control
The PLL can be enabled or disabled by the PLLEN register bit.
Table 46 PLLEN Control Bit
The WM8985 ADC high pass filter, ALC and DAC limiter characteristics are sample rate dependent.
SR should be set to the correct sample rate or the closest value if the actual sample rate is not
available.
If a sample rate that is not explicitly supported by the SR register settings is required then the
closest SR value to that sample rate should be chosen. The filter characteristics and the ALC attack
decay and hold times will scale appropriately.
The WM8985 has an on-chip phase-locked loop (PLL) circuit that can be used to:
Generate master clocks for the WM8985 audio functions from another external clock, e.g. in
telecoms applications.
Generate and output (on pin CSB/GPIO1) a clock for another part of the system that is derived from
an existing audio master clock.
Figure 38 shows the PLL and internal clocking on the WM8985.
R7 (07h)
Additional
Control
R1 (01h)
Power
management 1
REGISTER
ADDRESS
REGISTER
ADDRESS
3:1
BIT
5
BIT
SR
LABEL
PLLEN
LABEL
000
0
DEFAULT
DEFAULT
PLL enable
0 = PLL off
1 = PLL on
Approximate sample rate (configures the
coefficients for the internal digital filters):
000 = 48kHz
001 = 32kHz
010 = 24kHz
011 = 16kHz
100 = 12kHz
101 = 8kHz
110-111 = reserved
DESCRIPTION
DESCRIPTION
PD, Rev 4.6, July 2009
WM8985
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