WM8985GEFL Wolfson Microelectronics, WM8985GEFL Datasheet - Page 105

• Manufacturer Part Number: WM8985GEFL
• Description: Audio CODECs Multimedia CODEC with Class D HP
• Manufacturer: Wolfson Microelectronics

Specifications of WM8985GEFL

• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-32
• Minimum Operating Temperature: - 25 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Production Data
w
37 (25h)
38 (26h)
39 (27h)
41 (29h)
42 (2Ah)
43 (2Bh)
REGISTER
ADDRESS
4
3:0
8:6
5:0
8:0
8:0
8:4
3:0
8:6
5
4:3
2
1:0
8
7
6
5
4
BIT
PLLPRESCALE
PLLN[3:0]
PLLK[23:18]
PLLK[17:9]
PLLK[8:0]
DEPTH3D
OUT4_2ADCVOL
OUT4_2LNR
POBCTRL
BYPL2RMIX
BYPR2LMIX
LABEL
0
1000
000
01100
010010011
011101001
00000
0000
000
0
00
0
00
0
0
0
0
0
DEFAULT
0 = MCLK input not divided (default)
1 = Divide MCLK by 2 before input to PLL
Integer (N) part of PLL input/output frequency
ratio. Use values greater than 5 and less than
13.
Reserved. Initialise to 0
Fractional (K) part of PLL1 input/output
frequency ratio (treat as one 24-digit binary
number).
Fractional (K) part of PLL1 input/output
frequency ratio (treat as one 24-digit binary
number).
Fractional (K) part of PLL1 input/output
frequency ratio (treat as one 24-digit binary
number).
Reserved. Initialise to 0
Stereo depth
0000: 0% (minimum 3D effect)
0001: 6.67%
....
1110: 93.3%
1111: 100% (maximum 3D effect)
Controls the OUT4 to ADC input boost stage:
000 = Path disabled (disconnected)
001 = -12dB gain
010 = -9dB gain
011 = -6dB gain
100 = -3dB gain
101 = +0dB gain
110 = +3dB gain
111 = +6dB gain
OUT4 to L or R ADC input
0 = Right ADC input
1 = Left ADC input
Reserved. Initialise to 0
VMID independent current bias control
0 = Disable VMID independent current bias
1 = Enable VMID independent current bias
Reserved. Initialise to 0
Left bypass path (from the Left channel input
PGA stage) to right output mixer
0 = not selected
1 = selected
Right bypass path (from the right channel input
PGA stage) to Left output mixer
0 = not selected
1 = selected
Reserved. Initialise to 0
Reserved. Initialise to 0
Reserved. Initialise to 0
DESCRIPTION
PD, Rev 4.6, July 2009
Master Clock
and Phase
Locked Loop
(PLL)
Master Clock
and Phase
Locked Loop
(PLL)
Master Clock
and Phase
Locked Loop
(PLL)
Master Clock
and Phase
Locked Loop
(PLL)
Master Clock
and Phase
Locked Loop
(PLL)
3D Stereo
Enhancement
Analogue
Outputs
Analogue
Outputs
Analogue
Outputs
REFER TO
WM8985
105