M1AFS-EMBEDDED-KIT Actel, M1AFS-EMBEDDED-KIT Datasheet - Page 7

• Manufacturer Part Number: M1AFS-EMBEDDED-KIT
• Description: MCU, MPU & DSP Development Tools CortexM1-enabled Fusion Embedded Kit
• Manufacturer: Actel

Specifications of M1AFS-EMBEDDED-KIT

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 1 • Cortex-M1 Utilization and Performance Data (continued)
Utilization of Global Nets
Cortex-M1 configurations that do not include debug logic use
FPGA for the following signals:
Cortex-M1 configurations that do include debug logic use
for the following signals:
Layout Constraints
Actel's SmartDesign tool should be used to instantiate and configure Cortex-M1.
If you configure Cortex-M1 to enable debugging via the UJTAG macro (which is the necessary
configuration when debugging with Actel's SoftConsole tool), it is good practice to ensure that low skew
routing is used for the clock signal output from the UJTAG macro. You may also wish to use low skew
routing for the reset signal from the UJTAG macro, but this is a less critical signal. Debugging via UJTAG
is enabled by selecting the Include debug check box and setting the Debug interface option to JTAG,
using UJTAG macro in the Cortex-M1 configuration window.
The easiest way to ensure that low skew routing is used for the UJTAG clock signal is to select the
Instantiate CLKINT buffer for UJTAG clock signal check box in the Cortex-M1 configuration window.
Alternatively, you may wish to leave the Instantiate CLKINT buffer for UJTAG clock signal check box
cleared and instead use a PDC constraint file to ensure that low skew routing is used for the UJTAG
clock signal. For example, a constraint such as the following could be used to assign the UJTAG clock
Device
M1A3P1000
M1A3PE1500
M1A3PE3000
M1A3P600L
M1A3P1000L
M1A3PE3000L
Notes:
1. See
2. All frequency values are measured at commercial operating range conditions.
•
•
•
•
•
•
HCLK
SYSRESETn
HCLK
SYSRESETn
SWCLKTCK
DBGRESETn
Table 1-1 on page 10
Configuration
028910
028911
028910
028911
134820
134821
028910
028911
028910
028911
028910
028911
028910
028911
for a description of the numbers in the Configuration column.
Revision 12
Frequency (MHz)
66.26
63.65
65.61
63.80
48.38
62.34
62.03
53.42
52.13
55.09
52.68
51.03
50.76
46.35
four global clock nets within the FPGA
RAM Blocks
two global clock nets within the
28
28
4
4
4
4
4
4
4
4
4
4
4
4
Utilization
Cortex-M1 v3.1 Handbook
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