M1AFS-EMBEDDED-KIT Actel, M1AFS-EMBEDDED-KIT Datasheet - Page 22

• Manufacturer Part Number: M1AFS-EMBEDDED-KIT
• Description: MCU, MPU & DSP Development Tools CortexM1-enabled Fusion Embedded Kit
• Manufacturer: Actel

Specifications of M1AFS-EMBEDDED-KIT

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Cortex-M1 Features
22
Exception Types
The types of exceptions supported in Cortex-M1 are listed in
results from an error condition. Faults can be reported synchronously or asynchronously to the
instruction that caused them. In general, faults are reported synchronously. Faults caused by writes over
the bus are asynchronous faults. A synchronous fault is always reported with the instruction that caused
the fault. An asynchronous fault may vary in how it is reported with respect to the instruction that caused
the fault.
Table 3-1 • Cortex-M1 Exceptions
Exception Priority
In the processor exception model, priority determines when and how the processor handles exceptions.
Software priority levels can be assigned to interrupts.
The NVIC supports software-assigned priority levels. A priority level from 0 (highest) to 3 (lowest) can be
assigned to an interrupt by writing to the two-bit IP_N field in an Interrupt Priority Register. Hardware
priority ranges from
3, but hardware priority decreases with increasing interrupt number. The programmable priority level
overrides the hardware priority. For example, IRQ(4) would have a default priority lower than IRQ(2), but
if IRQ(4) is assigned a software priority of 1 and IRQ(2) is assigned 0, then IRQ(2) has priority over
IRQ(4).
Position
–
1
2
3
4
11
12
14
15
16
–
–
–
10
13
48
Exception
Hard Fault
maskable
Interrupt
Interrupt
PendSV
External
SysTick
SVCall
Reset
Type
Non-
–
–
–
–
3 (highest), to 3 (lowest). By default, external interrupts have a hardware priority of
Configurable System service call with SVC instruction.
Configurable Pendable request for system service. This is only
Configurable System tick timer has fired.
Configurable Asserted from outside the processor, IRQ[2
–
3 (highest) Invoked on power-up and warm reset. On first
Priority
–
–
–
–
–
2
1
Stack top is loaded from first entry of vector table
on reset.
instruction, drops to lowest priority. Thread mode.
Cannot be marked, prevented by activation, by
any other exception. Cannot be preempted by
any other exception other than Reset.
All classes of Fault
Reserved.
Reserved
pended by software.
and fed through the NVIC (prioritized).
R ev i sio n 1 2
Description
Table
3-1. A fault is an exception that
n-1
:0],
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
asynchronous
Synchronous
Synchronous
Activated
or
–
–
–