M1AFS-EMBEDDED-KIT Actel, M1AFS-EMBEDDED-KIT Datasheet - Page 12

• Manufacturer Part Number: M1AFS-EMBEDDED-KIT
• Description: MCU, MPU & DSP Development Tools CortexM1-enabled Fusion Embedded Kit
• Manufacturer: Actel

Specifications of M1AFS-EMBEDDED-KIT

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Cortex-M1 Overview
Delivery and Deployment
12
hover over a warning triangle with your mouse pointer, an information message will appear with an
explanation of how to resolve the issue.
Select or clear the Include debug check box to include or exclude debug logic. Selecting Include debug
enables the other debug related configuration options.
The Reset to debug logic (DBGRESETn) option is used to determine how the internal DBGRESETn
signal is driven. This signal is used to reset some debug components that are clocked by HCLK. Ideally,
Reset to debug logic (DBGRESETn) should be set to Driven by PORESETN input and a power-on
reset signal should be connected to the PORESETN input. Alternatively, NSYSRESET can be used as
the source for DBGRESETn by selecting Driven by NSYSRESET input, in which case PORESETN is
not used. The advantage of using a power-on reset signal as the source for DBGRESETn is that this
allows NSYSRESET to be asserted during a debug session without losing the debug connection to the
processor. NSYSRESET will often be connected to an external reset push-button.
Set the Debug interface option to JTAG, using UJTAG macro when using Actel's SoftConsole tool to
debug your Cortex-M1 system. When debugging with SoftConsole, the dedicated JTAG pins of the
device are used for the debug connection with the UJTAG macro used as a conduit between the
dedicated on-chip JTAG controller and the FPGA fabric where the Cortex-M1 resides. Set Debug
interface to JTAG, not using UJTAG macro when using a third party debugger such as ARM/Keil™
RealView
using UJTAG macro setting has been selected, the JTAG pins (TCK, TMS, TDI, TDO, and nTRST)
should be routed to appropriate device pins, which will typically be connected to a debug header. When
JTAG, using UJTAG macro has been selected, the JTAG pins must still be routed to the top level of your
design, but in this case specific pin assignments are not required. Actel's Designer tool will recognize that
the UJTAG macro is in use and make use of the dedicated JTAG pins of the device for the Cortex-M1
debug connection.
When Debug interface is set to JTAG, using UJTAG macro, two further check boxes are enabled for
selecting whether or not to instantiate CLKINT buffers for the UJTAG clock and reset signals.
Instantiating a CLKINT buffer is one way of ensuring that low skew routing is used for a signal.
Alternatively, design constraints may be used to cause low skew routing to be used. See the
Constraints" section on page 7
to be used for UJTAG signals. It is good practice to use low skew routing for the UJTAG clock signal, but
the use of low skew routing for the UJTAG reset signal is not as critical.
Cortex-M1 is available through the Libero
downloaded from a remote web-based repository and installed into the user's local vault, ready for use.
Once installed in Libero IDE, the core can be instantiated, configured, and generated within SmartDesign
for inclusion in your Libero IDE project.
Cortex-M1 I/O Ports
Table 1-2
Table 1-2 • Cortex-M1 Port Descriptions
Name
HCLK
NSYSRESET
PORESETN
HRESETn
WDOGRES
WDOGRESn
®
lists the ports of CortexM1Top, the top level of the core
or the IAR Systems
Width
1
1
1
1
1
1
Output Reset output to other components in the system
Output Reset signal to watchdog
Type
Input
Input
Input
Input
for more information on using PDC constraints to cause low skew routing
®
Embedded Workbench for ARM (EWARM) tool. When the JTAG, not
Main processor clock
Active low system reset.
Active low power on reset. This input is only used when the Reset
to debug logic (DBGRESETn) configuration option is set to
Driven by PORESETN input.
"Bark" signal from watchdog
R ev i sio n 1 2
®
Integrated Design Environment (IDE) IP Catalog. It can be
Description
.
"Layout