M1AFS-EMBEDDED-KIT Actel, M1AFS-EMBEDDED-KIT Datasheet - Page 24

• Manufacturer Part Number: M1AFS-EMBEDDED-KIT
• Description: MCU, MPU & DSP Development Tools CortexM1-enabled Fusion Embedded Kit
• Manufacturer: Actel

Specifications of M1AFS-EMBEDDED-KIT

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Cortex-M1 Features
Nested Vectored Interrupt Controller
24
Figure 3-4
Figure 3-4 • Exception Entry Without Wait States
After returning from the exception, the processor automatically pops the eight registers from the stack.
The interrupt return value, EXC_RETURN, passes as a data field in the LR, so exception functions can
be normal C/C++ functions and do not require a veneer.
The NVIC facilitates low-latency exception and interrupt handling and implements System Control
Registers. The NVIC supports reprioritizable interrupts. The NVIC and the processor core interface are
closely coupled, which enables low-latency interrupt processing and efficient processing of late arriving
interrupts. The NVIC registers are listed in
attempt to write a halfword or byte individually causes corruption of the register bits. All NVIC registers
and system debug registers are little-endian regardless of the endianness state of the processor.
Table 3-2 • Cortex-M1 NVIC Registers
The processor supports both level and pulse interrupts. A level interrupt is held asserted until it is cleared
by the ISR accessing the device. A pulse interrupt is a variant of an edge model. The edge must be
sampled on the rising edge of the processor clock (HCLK) instead of being asynchronous.
Name of Register
Irq 0 to 31 Set Enable Register
Irq to 31 Clear Enable Register
Irq to 31 Set Pending Register
Irq to 31 Clear Pending Register
Priority 0 Register
Priority 1 Register
Priority 2 Register
Priority 3 Register
Priority 4 Register
Priority 5 Register
Priority 6 Register
Priority 7 Register
TCMWDATA
TCMRDATA
TCMADDR
TCMWR
shows a timing example of an exception entry without wait states.
CLK
RIA
RI
9 Cycles
9 Cycles
SP + 28
xPSR
SP
R ev i sio n 1 2
Table 3-2
+4
r0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
+8
r1
+12
r2
and can only be accessed using word transfers. Any
+16
r3
+20
r12
r14
0xE000E40C
0xE000E41C
0xE000E100
0xE000E180
0xE000E200
0xE000E280
0xE000E400
0xE000E404
0xE000E408
0xE000E410
0xE000E414
0xE000E418
Address
+24
RA
RA
RC
Reset Value
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
RA + 4
LA
+4
LD