LPC1766-STK Olimex Ltd., LPC1766-STK Datasheet - Page 3

• Manufacturer Part Number: LPC1766-STK
• Description: MCU, MPU & DSP Development Tools DEV BRD FOR LPC1766 256KB FLASH 64KB RAM
• Manufacturer: Olimex Ltd.

Specifications of LPC1766-STK

• Processor To Be Evaluated: LPC1766
• Data Bus Width: 32 bit
• Interface Type: RS-232, Ethernet, USB, CAN, I2C, SPI, UART
• Dimensions: 134.6 mm x 101.6 mm
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ELECTROSTATIC WARNING:
BOARD USE REQUIREMENTS:
PROCESSOR FEATURES:
The LPC1766-STK board is shipped in protective anti-static packaging. The board
must not be subject to high electrostatic potentials. General practice for working
with static sensitive devices should be applied when working with this board.
Cables: The cable you will need depends on the programmer/debugger you use. If
you use ARM-JTAG-EW, you will need USB A-B cable. If you use a software
programmer such as FlashMagic, you will need RS232 cable.
Hardware:
programming/debugging tool if you work with EW-ARM.
You can use also ARM-USB-OCD, ARM-USB-TINY,
CrossWorks.or OpenOCD.
LPC1766-STK board use ARM 32-bit Cortex™-M3 microcontroller
LPC1766FBD100 from NXP Semiconductors with these features:
ARM Cortex-M3 processor, running at frequencies of up to 100 MHz. A
Memory Protection Unit (MPU) supporting eight regions is included.
ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
256 kB on-chip flash programming memory. Enhanced flash memory
accelerator enables high-speed 100 MHz operation with zero wait states.
In-System Programming (ISP) and In-Application Programming (IAP) via on-
chip bootloader software.
On-chip SRAM includes:
Eight channel General Purpose DMA controller (GPDMA) on the AHB
multilayer matrix that can be used with the SSP, I2S-bus, UART, the Analog-to-
Digital and Digital-to-Analog converter peripherals, timer match signals, and
for memory-to-memory transfers.
Multilayer AHB matrix interconnect provides a separate bus for each AHB
master. AHB masters include the CPU, General Purpose DMA controller,
Ethernet MAC, and the USB nterface. This interconnect provides
communication with no arbitration delays.
32 kB of SRAM on the CPU with local code/data bus for high-
performance CPU access.
Two 16 kB SRAM blocks with separate access paths for higher
throughput. These SRAM blocks may be used for Ethernet, USB, and
DMA memory, as well as for general purpose CPU instruction and
data storage.
Programmer/Debugger
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ARM-JTAG-EW
ARM-USB-TINY-H
or other compatible
with