S1D13743F00A200 Epson, S1D13743F00A200 Datasheet - Page 47

• Manufacturer Part Number: S1D13743F00A200
• Description: LCD Drivers LCD CNTRL w/Embedded 464KB SRAM
• Manufacturer: Epson

Specifications of S1D13743F00A200

• Maximum Clock Frequency: 33 MHz, 68.59 MHz
• Operating Supply Voltage: 1.5 V
• Maximum Operating Temperature: + 85 C
• Package / Case: QFP-20-144
• Attached Touch Screen: No
• Maximum Supply Current: 74 mA
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Epson Research and Development
Vancouver Design Center
10.3.2 Clock Configuration Registers
bit 7
bits 5-0
Hardware Functional Specification
Issue Date: 2010/05/18
REG[04h] PLL M-Divider Register
Default = 00h
PLL Lock (RO)
7
n/a
6
Note
Note
PLL Lock (Read Only)
This bit indicates the status of the PLL output.
When this bit = 0, the PLL output is not stable. In this state read/write access to the display
buffer is prohibited.
When this bit = 1, the PLL output is stable.
M-Divider bits [5:0]
These bits determine the divide ratio between CLKI and the actual input clock to the PLL
The internal input clock to the PLL (PLLCLK) must be between 1 MHz and 2 MHz. De-
pending on CLKI, these bits will have to be set accordingly.
Values higher than 20h are not allowed.
5
Table 10-2: PLL M-Divide Selection
REG[04h] Bits 5-0
21h to 3Fh
01h
02h
03h
20h
0h
•
•
•
4
Revision 2.7
M-Divide Ratio
Reserved
3
M-Divider bits 5-0
33:1
1:1
2:1
3:1
4:1
•
•
•
2
1
Read/Write
X70A-A-001-02
S1D13743
0
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