XRT94L31IB-L Exar Corporation, XRT94L31IB-L Datasheet - Page 8

• Manufacturer Part Number: XRT94L31IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L31IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L31
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
PIN DESCRIPTION OF THE XRT94L31 (REV. B)
PIN #
AE27
U2
U1
P3
P2
RXCLK_19MHZ
SIGNAL NAME
RXLDAT_R_N
RXLDAT_R_P
REFCLK_P
REFCLK_N
I/O
O
I
I
I
I
LVPEC
L
LVPEC
L
CMOS
LVPEC
L
LVPEC
L
TYPE
Receive STS-3/STM-1 Data - Positive Polarity PECL Input - Redun-
dant Port:
This input pin, along with RXLDAT_R_N functions as the Recovered
Data Input, from the Optical Transceiver or as the Receive Data Input
from the system back-plane.
N
Receive STS-3/STM-1 Data - Negative Polarity PECL Input - Redun-
dant Port:
This input pin, along with RXLDAT_R_P functions as the Recovered
Data Input, from the Optical Transceiver or as the Receive Data Input
from the system back-plane.
N
19.44MHz Recovered Output Clock:
This pin outputs a 19.44MHz clock signal that has been derived from the
incoming STS-3/STM-1 LVPECL line signal (via the Receive STS-3/
STM-1 PECL Interface block) and has been extracted out and derived
by Clock and Data Recovery PLL (within the Receive STS-3/STM-1
PECL Interface block).
To operate the STS-3/STM-1 Interface of the XRT94L31 in the loop-tim-
ing mode, route this particular output signal through a narrow-band PLL
(in order to attenuate any jitter within this signal) prior to routing it to the
REFTTL input pin.
Transmit Reference Clock - Positive Polarity PECL Input:
This input pin, along with REFCLK_N and REFTTL can be configured to
function as the timing source for the STS-3/STM-1 Transmit Interface
Block.
If these two input pins are configured to function as the timing source, a
155.52MHz clock signal must be applied to these input pins in the form
of a PECL signal. Configure these two inputs to function as the timing
source by writing the appropriate data into the Transmit Line Interface
Control Register (Address Location = 0x0383)
N
Transmit Reference Clock - Negative Polarity PECL Input:
This input pin, along with REFCLK_P and REFTTL can be configured to
function as the timing source for the STS-3/STM-1 Transmit Interface
Block.
If these two input pins are configured to function as the timing source,
then the user must apply a 155.52MHz clock signal, in the form of a
PECL signal to these input pins. These two inputscan be configured to
function as the timing source by writing the appropriate data into the
Transmit Line Interface Control Register (Address Location = 0x0383).
N
OTE
OTE
OTE
OTE
: For APS (Automatic Protection Switching) purposes, this input
: For APS (Automatic Protection Switching) purposes, this input
: If REFTTL clock input is used, set this pin to a logic "High"
: Set this pin to a logic "Low" if REFTTL clock input is used
pin, along with RXLDAT_R_N functions as the Redundant
Receive STS-3/STM-1 Data Input Port.
pin, along with RXLDAT_R_N functions as the Redundant
Receive STS-3/STM-1 Data Input Port.
8
DESCRIPTION
REV. 1.0.1