XRT94L31IB-L Exar Corporation, XRT94L31IB-L Datasheet - Page 130

• Manufacturer Part Number: XRT94L31IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L31IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L31
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
GENERAL DESCRIPTION ................................................................................................ 1
1.0 ELECTRICAL CHARACTERISTIC INFORMATION FOR THE XRT94L31 DEVICE ............................ 96
APPLICATIONS .......................................................................................................................................... 1
FEATURES ................................................................................................................................................. 1
ORDERING INFORMATION....................................................................................................................... 2
PIN DESCRIPTION
1.1 DC ELECTRICAL CHARACTERISTIC INFORMATION ................................................................................... 96
1.2 AC ELECTRICAL CHARACTERISTIC INFORMATION - MICROPROCESSOR INTERFACE TIMING .......... 96
1.3 STS-3/STM-1 TELECOM BUS INTERFACE TIMING INFORMATION ........................................................... 107
F
T
T
F
F
T
F
F
T
F
F
T
F
F
T
F
F
T
F
F
T
F
T
F
T
F
T
T
IGURE
ABLE
ABLE
IGURE
IGURE
ABLE
IGURE
IGURE
ABLE
IGURE
IGURE
ABLE
IGURE
IGURE
ABLE
IGURE
IGURE
ABLE
IGURE
IGURE
ABLE
IGURE
ABLE
IGURE
ABLE
IGURE
ABLE
ABLE
1.2.1 MICROPROCESSOR INTERFACE TIMING - ASYNCHRONOUS INTEL MODE........................................................ 96
1.2.2 MICROPROCESSOR INTERFACE TIMING - ASYNCHRONOUS MOTOROLA (68K) MODE ................................... 98
1.2.3 MICROPROCESSOR INTERFACE TIMING - POWER PC 403 SYNCHRONOUS MODE ........................................ 100
1.2.4 MICROPROCESSOR INTERFACE TIMING - IDT3051/52 MODE ............................................................................. 103
1.2.5 MICROPROCESSOR INTERFACE TIMING - MPC860 MODE .................................................................................. 105
1.3.1 STS-3/STM-1 TELECOM BUS INTERFACE TIMING INFORMATION ...................................................................... 107
1.3.2 STS-3/STM-1 PECL INTERFACE TIMING INFORMATION ....................................................................................... 109
1.3.3 DS3/E3/STS-1 LIU INTERFACE TIMING INFORMATION ......................................................................................... 110
1.3.4 INGRESS TIMING FOR DS3/E3 APPLICATIONS ..................................................................................................... 111
5: T
6: T
11: T
12: T
1: DC C
2: DC C
3: T
4: T
7: T
8: T
9: T
10: T
13. A
1. B
2. A
3. A
4. A
5. A
6. S
7. S
8. S
9. S
10. MPC860 M
11. MPC860 M
12. A
14. A
15. A
16. A
1.3.1.1 T
1.3.1.2 T
1.3.2.1 T
1.3.3.1 I
96
M
CHRONOUS
IMING
102
IMING
104
I
T
TERFACE
110
FACE
STS_1_CLOCK_IN) .................................................................................................................................................. 111
STS_1_CLOCK_IN) .................................................................................................................................................. 111
IMING
IMING
IMING
IMING
NTERFACE
IMING
RANSMIT
IMING
IMING
LOCK
SYNCHRONOUS
SYNCHRONOUS
SYNCHRONOUS
SYNCHRONOUS
YNCHRONOUS
YNCHRONOUS
YCHRONOUS
YCHRONOUS
IMING
ODE
N
N
N
N
N
HARACTERISTIC
HARACTERISTICS
I
I
I
I
I
LLUSTRATION OF THE TIMING RELATIONSHIPS BETWEEN THE
LLUSTRATION OF THE
LLUSTRATION OF THE
LLUSTRATION OF THE
LLUSTRATION OF THE
(
I
I
I
I
I
I
NGRESS
IN THE
NFORMATION FOR THE
NFORMATION FOR THE
NFORMATION FOR THE
NFORMATION FOR THE
NFORMATION FOR THE
HE
NFORMATION FOR THE
HE
I
HE
........................................................................................................................................................................... 98
D
I
I
NFORMATION FOR THE
I
NFORMATION FOR THE
NFORMATION FOR THE
NFORMATION FOR THE
IAGRAM OF THE
..................................................................................................................................................................... 109
T
R
R
STS-3/STM-1 T
. ................................................................................................................................................................. 107
M
OF THE
RANSMIT
ECEIVE
ECEIVE
ODE
ODE
ODE
I
NGRESS
M
M
DS3/E3/STS-1 I
M
M
ODE
ODE
M
M
M
M
ODE
ODE
- T
- T
.......................................................................................................................................................... 99
ODE
ODE
ODE
ODE
STS-3/STM-1 T
STS-3/STM-1 PECL I
(A
IMING
IMING
4 - IDT3051/52 I
4 - IDT3051/52 I
STS-3/STM-1 T
XRT94L31 (R
(A
3 - IBM P
3 - IBM P
D
PPLIES TO ALL
1 - I
1 - I
2 - M
2 - M
PPLIES TO ALL
IRECTION
XRT94L31 ............................................................................................................................... 2
(W
(R
W
ELECOM
W
W
W
NTEL
NTEL
M
M
OTOROLA
OTOROLA
AVEFORMS OF THE
AVEFORMS OF THE
AVEFORMS OF THE
AVEFORMS OF THE
EAD
M
M
M
T
RITE
R
I
ICROPROCESSOR
ICROPROCESSOR
I
R
NGRESS
RANSMIT
NGRESS
ICROPROCESSOR
ICROPROCESSOR
ICROPROCESSOR
TABLE OF CONTENTS
NTERFACE
ECEIVE
OWER
OWER
ECEIVE
T
T
) .............................................................................................................................. 111
C
YPE
YPE
C
YCLE
B
ELECOM
YCLE
US
TTL-L
ELECOM
PC 403 I
PC 403 I
NTERFACE
NTERFACE
LVPECL I
(68K) P
(68K) P
P
P
EV
STS-3/STM-1 T
DS3/E3/STS-1 LIU I
DS3/E3/STS-1 LIU I
STS-3/STM-1 T
STS-3/STM-1 PECL I
).................................................................................................................... 106
I
ROGRAMMED
ROGRAMMED
NTERFACE
) .................................................................................................................. 105
NTERFACE
. B) ........................................................................................ 3
T
EVEL
IMING
B
B
US
ROGRAMMED
ROGRAMMED
NTERFACE
NTERFACE
I
I
US
S
S
S
DS3/E3/STS-1
NTERFACE
NTERFACE
I
I
I
NPUT AND
T
T
I
NTERFACE
NTERFACE WHEN CONFIGURED TO OPERATE IN THE
NTERFACE
IGNALS THAT ARE OUTPUT VIA THE
IGNALS THAT ARE
IGNALS THAT ARE
NPUT AND
I
....................................................................................................... 110
IMING
IMING
NTERFACE
I
.................................................................................................... 108
NTERFACE
T
I
I/O T
I/O T
IMING
ELECOM
ELECOM
(W
(R
T
T
,
,
EAD
O
IMING
IMING
,
WHEN CONFIGURED TO OPERATE IN THE
RITE
WHEN CONFIGURED TO OPERATE IN THE
,
IMING
IMING
CMOS L
NTERFACE FOR
I/O T
I/O T
....................................................................................... 109
NTERFACE FOR
WHEN CONFIGURED TO OPERATE IN THE
WHEN CONFIGURED TO OPERATE IN THE
UTPUT PINS
T
NTERFACE
T
IMING
T
C
SIGNALS THAT ARE INPUT TO THE
IMING
C
X
B
B
YCLE
(W
(R
IMING
IMING
SBFP
(W
(W
YCLE
US
US
I
I
EAD
NPUT VIA THE
NPUT VIA THE
RITE
RITE
RITE
.......................................................................... 108
EVEL
I
I
NTERFACE
) ...................................................................... 104
........................................................................ 107
NTERFACE
)..................................................................... 103
(W
(R
INPUT PIN AND THE
) ..................................................................... 96
C
C
.................................................................... 110
C
C
YCLE
EAD
O
RITE
YCLE
YCLE
YCLE
DS3/E3 A
DS3/E3 A
UTPUT PINS
C
)........................................................... 97
C
) ......................................................... 97
YCLE
)....................................................... 100
)....................................................... 101
........................................................ 109
YCLE
R
R
....................................................... 108
ECEIVE
ECEIVE
T
) ................................................. 99
RANSMIT
PPLICATIONS
PPLICATIONS
)................................................ 98
- A
T
STS-3/STM-1 T
STS-3/STM-1 PECL I
MBIENT
X
A_CLK
STS-3/STM-1 T
DS3/E3/STS-1 LIU I
(
IBM P
IBM P
FALLING EDGE OF
T
(
M
RISING EDGE OF
I
MPC860 M
EMPERATURE
NTEL
OUTPUT PIN WITHIN THE
OTOROLA
OWER
OWER
A
ELECOM
SYNCHRONOUS
PC403 M
PC403 M
ELECOM
(68K) A
ODE
REV. 1.0.1
NTERFACE
= 25°C)
B
DS3/E3/
DS3/E3/
. 106
US
NTER
B
SYN
ODE
ODE
US
I
N
-
-
-