XRT94L31IB-L Exar Corporation, XRT94L31IB-L Datasheet - Page 60

• Manufacturer Part Number: XRT94L31IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L31IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L31
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
PIN DESCRIPTION OF THE XRT94L31 (REV. B)
PIN #
AD15
TXHDLCDAT_2_1
STS1TXA_2_D1
SIGNAL NAME
TXGFC_2
I/O
I
TTL
TYPE
Transmit STS-1 Telecom Bus Interface - Channel 2 - Data Bus Input pin
number 1/Transmit High-Speed HDLC Controller Input Interface block -
Input Data Bus - Pin 1:
The function of this pin depends upon whether or not the STS-1 Telecom
Bus Interface, associated with Channel 2 is enabled.
If STS-1 Telecom Bus (Channel 2) has been enabled - Transmit STS-
1 Telecom Bus Interface - Input Data Bus pin number 1 -
STS1TxA_2_D1:
This input pin along with STS1TXA_2_D[7:2] and STS1TXA_2_D0 func-
tions as the Transmit (Add) STS-1 Telecom Bus Interface - Input Data
Bus for Channel 2. The Transmit STS-1 Telecom Bus interface will sam-
ple and latch this pin upon the falling edge of STS1TXA_CLK_2.
If the STS-1 Telecom Bus Interface (associated with Channel 2) has
been disabled:
This input pin can function in either of the following roles, depending
upon which mode the XRT94L31 has been configured to operate in.
If the XRT94L31 has been configured to operate in the High-Speed
HDLC Controller over DS3/STS-3 Mode - Transmit High-Speed
HDLC Controller Input Interface block - Channel 2 - Data Bus Input
pin # 2 - TXHDLCDAT_2_1:
In this mode this input pin will function as Bit 1 within the Transmit High-
Speed HDLC Controller Input Interface block - Input Data Bus (e.g., the
TxHDLCDat_2[7:0] input pins).The Transmit High-Speed HDLC Control-
ler Input Interface block will provide the System-Side Terminal equip-
ment with a byte-wide Transmit High-Speed HDLC Controlller clock
output signal (TxHDLCClk_2). The Transmit High-Speed HDLC Control-
ler Input Interface block will sample the data residing on this input pin
(along with the rest of the TxHDLCDat_2[7:0] input pins) upon the rising
edge of the TxHDLCClk_2 clock output signal.
If the XRT94L31 has been configured to operate in the ATM UNI
Mode
- TXGFC_2 (Transmit GFC data - Channel 2)
If the XRT94L31 has been configured to operate in the 3-Channel
DS3/E3/STS-1 to STS-3/STM-1 Mapper Mode
- NO FUNCTION:
Tie this input pin to GND.
60
DESCRIPTION
REV. 1.0.1