XRT94L31IB-L Exar Corporation, XRT94L31IB-L Datasheet - Page 46

• Manufacturer Part Number: XRT94L31IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L31IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L31
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
PIN DESCRIPTION OF THE XRT94L31 (REV. B)
PIN #
A12
TXHDLCDAT_0_4
TXDS3OHIND_0
STS1TXA_0_D4
SIGNAL NAME
I/O
IO
TTL/
CMOS
TYPE
Transmit STS-1 Telecom Bus Interface - Channel 0 - Data Bus Input
pin number 4/Transmit High-Speed HDLC Controller Input Interface
block - Channel 0 - Input Data Bus - Pin 4/Transmit DS3/E3 Over-
head Indicator Output - Channel 0:
The function of this pin depends upon whether or not the STS-1 Telecom
Bus Interface, associated with Channel 0 is enabled.
If STS-1 Telecom Bus (Channel 0) has been enabled - Transmit STS-
1 Telecom Bus Interface - Input Data Bus pin number 4 -
STS1TXA_0_D4:
This input pin along with STS1TXA_0_D[7:5] and STS1TXA_0_D[3:0]
function as the Transmit (Add) STS-1 Telecom Bus Interface - Input
Data Bus for Channel 0. The Transmit STS-1 Telecom Bus interface will
sample and latch this pin upon the falling edge of STS1TXA_CLK_0.
If the STS-1 Telecom Bus Interface (associated with Channel 0) has
been disabled:
This input/output pin can function in either of the following roles, depend-
ing upon which mode the XRT94L31 has been configured to operate in,
as described below.
If the XRT94L31 has been configured to operate in the High-Speed
HDLC Controller over DS3/STS-3 Mode - Transmit High-Speed
HDLC Controller Input Interface block - Channel 0 - Data Bus Input
pin # 4 - TxHDLCDATA_0_4:
If the XRT94L31 is configured to operate in the High-Speed HDLC Con-
troller over DS3/STS-3 Mode, then this input pin will function as Bit 4
within the Transmit High-Speed HDLC Controller Input Interface block -
Input Data Bus (e.g., the TxHDLCDat_0[7:0] input pins).
The Transmit High-Speed HDLC Controller Input Interface block will pro-
vide the System-Side Terminal equipment with a byte-wide Transmit
High-Speed HDLC Controlller clock output signal (TxHDLCClk_0). The
Transmit High-Speed HDLC Controller Input Interface block will sample
the data residing on this input pin (along with the rest of the
TxHDLCDat_0[7:0] input pins) upon the rising edge of the TxHDLCClk_0
clock output signal.
If the XRT94L31 is configured to operate in the Clear-Channel DS3/
E3 Framer over STS-3/STM-1 Mapper Mode - Transmit DS3/E3 Over-
head Indicator Output - Channel 0 - TxDS3OHInd_0:
If the XRT94L31 has been configured to operate in the Clear-Channel
Framer over STS-3/STM-1 Mapper Mode, then this output pin can be
configured to functions as the transmit overhead data indicator for the
System-Side terminal equipment, or as a Gapped-Clock output for the
Transmit Payload Data Input Interface. This output pin is pulsed "High"
for one DS3 or E3 bit period in order to indicate (to the System-Side ter-
minal equipment) that the Transmit Section of the Framer is going to be
processing an overhead bit, upon the next rising edge of TxInClk_0, and
will NOT latch the data that is applied to the TxDS3DATA_0 input pin.
46
DESCRIPTION
REV. 1.0.1