XRT94L31IB-L Exar Corporation, XRT94L31IB-L Datasheet - Page 24

• Manufacturer Part Number: XRT94L31IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L31IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L31
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
PIN DESCRIPTION OF THE XRT94L31 (REV. B)
PIN #
E9
C6
A4
TxE1F1E2Enable
TxE1F1E2Frame
SIGNAL NAME
TxE1F1E2
I/O
O
O
I
CMOS
CMOS
TTL
TYPE
Transmit E1-F1-E2 Byte Input Port - Enable (or Ready) Indicator
Output pin:
This output pin, along with the TxTOHClk output pin and the TxE1F1E2
input pin is used to insert their value for the E1, F1 and E2 bytes, into the
Transmit STS-3 TOH Processor Block. The Transmit STS-3 TOH Pro-
cessor block will accept this data and will insert into the E1, F1 and E2
byte-fields, within the outbound STS-3 data-stream.
Whatever external circuitry (which is connected to the TxTOHClk, the
TxE1F1E2 and this output pin), is suppose to do the following.
It should continuously monitor the state of this output pin.
Whenever this output pin pulses "High", then the external circuitry
should place the next orderwire bit (to be inserted into the Transmit STS-
3 TOH Processor block) onto the TxE1F1E2 input pin, upon the rising
edge of TxTOHClk.
Any data that is placed on the TxE1F1E2 input pin, will be sampled upon
the falling edge of TxOHClk.
Transmit E1-F1-E2 Byte Input Port - Framing Output Pin.
This output pin pulses "High" for one period of TxTOHClk, one TxTO-
HClk bit-period prior to the Transmit E1-F1-E2 Byte Input Port expecting
the very first byte of the E1 byte, within a given outbound STS-3 frame.
Transmit E1-F1-E2 Byte Input Port - Input Pin:
This input pin, along with the TxE1F1E2Enable and the TxTOHClk out-
put pins are used to insert their value for the E1, F1 and E2 bytes, into
the Transmit STS-3 TOH Processor Block. The Transmit STS-3 TOH
Processor block will accept this data and insert it into the E1, F1 and E2
byte fields, within the outbound STS-3 data-stream.
Whatever external circuitry that is interfaced to this input pin, the
TxE1F1E2Enable and the TxTOHClk pins is suppose to do the following.
It should continuously monitor the state of the TxE1F1E2Enable input
pin.
Whenever the TxE1F1E2Enable input pin pulses "High", then the exter-
nal circuitry should place the next orderwire bit (to be inserted into the
Transmit STS-3 TOH Processor block) onto this input pin upon the rising
edge of TxTOHClk.
Any data that is placed on the TxE1F1E2 input pin, will be sampled upon
the falling edge of TxTOHClk.Note:
N
OTE
: This pin should be connected to GND if it is not used.
24
DESCRIPTION
REV. 1.0.1