XRT94L31IB Exar Corporation, XRT94L31IB Datasheet - Page 63

• Manufacturer Part Number: XRT94L31IB
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L31IB

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Product: Mapper
• Lead Free Status / RoHS Status: Contains lead / RoHS Compliant

REV. 1.0.1
PIN DESCRIPTION OF THE XRT94L31 (REV. B)
AG17
PIN #
TXHDLCDAT_2_4
TXDS3OHIND_2
STS1TXA_2_D4
SIGNAL NAME
I/O
I/O
TTL/
CMOS
TYPE
Transmit STS-1 Telecom Bus Interface - Channel 2 - Data Bus Input
pin number 4/Transmit High-Speed HDLC Controller Input Interface
block - Channel 2 - Input Data Bus - Pin 4/Transmit DS3/E3 Over-
head Indicator Output - Channel 2:
The function of this pin depends upon whether or not the STS-1 Telecom
Bus Interface, associated with Channel 2 is enabled.
If STS-1 Telecom Bus (Channel 2) has been enabled - Transmit STS-
1 Telecom Bus Interface - Input Data Bus pin number 4 -
STS1TXA_2_D4:
This input pin along with STS1TXA_2_D[7:5] and STS1TXA_2_D[3:0]
function as the Transmit (Add) STS-1 Telecom Bus Interface - Input Data
Bus for Channel 2. The Transmit STS-1 Telecom Bus interface will sam-
ple and latch this pin upon the falling edge of STS1TXA_CLK_2.
If the STS-1 Telecom Bus Interface (associated with Channel 2) has
been disabled:
This input/output pin can function in either of the following roles, depend-
ing upon which mode the XRT94L31 has been configured to operate in,
as described below.
If the XRT94L31 has been configured to operate in the High-Speed
HDLC Controller over DS3/STS-3 Mode - Transmit High-Speed
HDLC Controller Input Interface block - Channel 2 - Data Bus Input
Pin # 4 -TXHDLCDAT_2_4:
in this configuration, this input pin will function as Bit 4 within the Trans-
mit High-Speed HDLC Controller Input Interface block - Input Data Bus
(e.g., the TxHDLCDat_2[7:0] input pins).
The Transmit High-Speed HDLC Controller Input Interface block will pro-
vide the System-Side Terminal equipment with a byte-wide Transmit
High-Speed HDLC Controlller clock output signal (TxHDLCClk_2). The
Transmit High-Speed HDLC Controller Input Interface block will sample
the data residing on this input pin (along with the rest of the
TxHDLCDat_2[7:0] input pins) upon the rising edge of the TxHDLCClk_2
clock output signal.
If the XRT94L31 is configured to operate in the Clear-Channel DS3/
E3 Framer over STS-3/STM-1 Mapper Mode - Transmit DS3/E3 Over-
head Indicator Output - Channel 2 - TXDS3OHIND_2:
This output pin will pulse "High" one bit-period prior to the time that the
DS3/E3 Frame Generator block (within Channel 2) will be processing an
Overhead bit. The purpose of this outpout pin is to warn the Terminal
Equipment that, during the very next bit-period, the DS3/E3 Frame Gen-
erator block is going to be processing an Overhead Bit and will be ignor-
ing any data that is applied to to the TxDS3DATA_2 input pin.
N
OTE
: This output pin can be ignored provide that either the Primary or
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
Secondary Frame Synchronizer block is always up-stream from
the DS3/E3 Frame Generator block.
63
DESCRIPTION
XRT94L31