XRT94L31IB Exar Corporation, XRT94L31IB Datasheet - Page 41

• Manufacturer Part Number: XRT94L31IB
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L31IB

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Product: Mapper
• Lead Free Status / RoHS Status: Contains lead / RoHS Compliant

REV. 1.0.1
PIN DESCRIPTION OF THE XRT94L31 (REV. B)
PIN #
B13
TXHDLCDAT_0_0
STS1TXA_0_D0
SIGNAL NAME
TXGFCMSB_0
I/O
I/O
TTL/
CMOS
TYPE
Transmit STS-1 Telecom Bus Interface - Channel 0 - Data Bus Input
pin number 0/Transmit High-Speed HDLC Controller Input Interface
block - Channel 0 - Input Data Bus - Pin 0:
The function of this pin depends upon whether or not the STS-1 Telecom
Bus Interface, associated with Channel n is enabled.
If STS-1 Telecom Bus (Channel n) has been enabled -Transmit STS-
1 Telecom Bus Interface - Input Data Bus pin number 0 -
STS1TxA_0_D0:
This input pin along with STS1TXA_D_0[7:1] function as the Transmit
(Add) STS-1 Telecom Bus Interface - Input Data Bus for Channel 0. This
particular input pin functions as the LSB (Least Significant Bit) input pin
on the Transmit (Add) STS-1 Telecom Bus Interface - Input Data Bus.
The Transmit STS-1 Telecom Bus interface will sample and latch this pin
upon the falling edge of STS1TXA_CLK_0.
The LSB of any byte (within the incoming STS-1/STS-3 or STM-1 sig-
nal), which is being input into the Transmit STS-1 Telecom Bus - Input
Data Bus (for Channel 0) should be input via this pin.
If the STS-1 Telecom Bus Interface (associated with Channel 0) has
been disabled:
This input pin can function in either of the following roles, depending
upon which mode the XRT94L31 has been configured to operate in, as
described below.
If the XRT94L31 has been configured to operate in the High-Speed
HDLC Controller over DS3/STS-3 Mode - Transmit High-Speed HDLC
Controller Input Interface block - Channel 0 - Data Bus Input pin # 0 -
TxHDLCDAT_0_0:
If the XRT94L31 is configured to operate in the High-Speed HDLC
Controller over DS3/STS-3 Mode, then this input pin will function as
Bit 0 (the LSB) within the Transmit High-Speed HDLC Controller
Input Interface block - Input Data Bus (e.g., the TxHDLCData_0[7:0]
input pins).
The Transmit High-Speed HDLC Controller Input Interface block will pro-
vide the System-Side Terminal equipment with a byte-wide Transmit
High-Speed HDLC Controlller clock output signal (TxHDLCClk_0). The
Transmit High-Speed HDLC Controller Input Interface block will sample
the data residing on this input pin (along with the rest of the
TxHDLCData_0[7:0] input pins) upon the rising edge of the
TxHDLCClk_0 clock output signal.
If the XRT94L31 has been configured to operate in the ATM UNI
Mode
- TXGFCMSB_0 (Transmit GFC MSB Indicator - Channel 0)
- TXGFC_0 (Transmit GFC data - Channel 0)
- TXCELLTXED_0 (Cell Transmitted - Channel 0)
This input pin will only function in this role if the XRT94L31 has been
configured to operate in the ATM UNI Mode.
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
41
DESCRIPTION
XRT94L31