XRT94L31IB Exar Corporation, XRT94L31IB Datasheet - Page 36

• Manufacturer Part Number: XRT94L31IB
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L31IB

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Product: Mapper
• Lead Free Status / RoHS Status: Contains lead / RoHS Compliant

XRT94L31
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
PIN DESCRIPTION OF THE XRT94L31 (REV. B)
PIN #
AC14
M27
C14
E19
TXUCLK/TXPCLK
STS1TXA_CK_0
STS1TXA_CK_1
STS1TXA_CK_2
TXSENDFCS_0
TXSENDFCS_1
TXSENDFCS_2
SIGNAL NAME
TXGFCCLK_0
TXGFCCLK_1
TXGFCCLK_2
STS-1 TELECOM BUS INTERFACE - TRANSMIT DIRECTION
I/O
O
I
I
I
TTL
TTL
TTL
CMOS
TYPE
For Mapper applications, please connect this pin to GND.
STS-1 Transmit Telecom Bus Clock Input pin/Transmit High-Speed
HDLC Controller Input Interface Block - Send FCS Command Input
pin - Channel n (n=0,1,2):
The function of this input pin depends upon whether or not the STS-1
Telecom Bus Interface for Channel n has been enabled.
If STS-1 Telecom Bus (Channel n) has been enabled -
STS1TXA_CLK_[0:3] - Transmit STS-1 Telecom Bus Interface Block
Transmit Clock Input - Channel n:
This input clock signal functions as the clock source for the Transmit
STS-1 Telecom Bus, associated with Channel n. All input signals (e.g.,
STS1TXA_ALARM_n, STS1TXA_D_n[7:0], STS1TXA_DP_n,
STS1TXA_PL_n, STS1TXA_C1J1_n) are sampled upon the falling edge
of this input clock signal.This clock signal should operate at 19.44MHz.
(For STS-3 mode) or 6.48MHz (for STS-1 mode).
If STS-1 Telecom Bus (Channel n) has NOT been enabled:
If STS-1 Telecom Bus (Channel n) has not been enabled, then this par-
ticular pin can be configured to function in either of the following roles.
TXSENDFCS_n (Transmit High-Speed HDLC Controller Input Inter-
face block Send FCS Command Input - Channel n - High-Speed
HDLC Controller Mode Only)
The user's terminal equipment is expected to control both this input pin
and the TXSENDMSG_0 input pin during the construction and transmis-
sion of each outbound HDLC frame.
This input pin is used to command the Transmit HDLC Controller block
to compute and insert the computed FCS value into the back-end of the
outbound HDLC frame as a trailer.
If the user has configured the Transmit HDLC Controller to compute and
insert a CRC-16 value into the outbound HDLC frame, then the terminal
equipment is expected to pull this input pin "High" for two periods of
TxHDLCClk_n.
Likewise, if the user has configured the Transmit HDLC Controller to
compute and insert a CRC-32 value into the outbound HDLC frame,
then the terminal equipment is expected to pull this input pin "High" for
four periods of TxHDLCClk_n.
TXGFCCLK_n (Transmit GFC Nibble-Field Input Port clock signal
Input) - ATM Applications ONLY.
This pin only functions in this particular role if the XRT94L31 has been
configured to operate in the ATM UNI Mode.
N
OTE
: The user should tie this pin to GND if the DS3/E3 Framer block
has NOT been configured to operate in the High-Speed HDLC
Controller Mode.
36
DESCRIPTION
REV. 1.0.1