PIC18F87J72-I/PT Microchip Technology, PIC18F87J72-I/PT Datasheet - Page 454

• Manufacturer Part Number: PIC18F87J72-I/PT
• Description: IC PIC MCU 8BIT 14KB FLSH 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F87J72-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 80-TQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: SPI, USART, SPI, I2C
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 14
• Controller Family/series: PIC18F
• No. Of I/o's: 51
• Ram Memory Size: 3923Byte
• Cpu Speed: 48MHz
• No. Of Timers: 4
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F87J72 FAMILY
B.5.9
To signify when channel data is ready for transmission,
the data ready signal is available on the Data Ready pin
(DR) through an active-low pulse at the end of a
channel conversion.
The Data Ready pin outputs an active-low pulse with a
period that is equal to the DRCLK clock period and with
a width equal to one DMCLK period.
When not active-low, this pin can either be in high
impedance (when DR_HIZN = 0) or in a defined logic
high state (when DR_HIZN = 1). This is controlled
through the Configuration registers. This allows multiple
devices to share the same Data Ready pin (with a
pull-up resistor connected between DR and DV
3-phase energy meter designs to reduce microcontroller
pin count. A single device on the bus does not require a
pull-up resistor.
After a data ready pulse has occurred, the ADC output
data can be read through SPI communication. Two sets
of latches at the output of the ADC prevent the
communication from outputting corrupted data (see
Section B.5.9.1 “Data Ready Latches And Data
Ready Modes (DRMODE<1:0>)”).
The CS pin has no effect on the DR pin, which means
even if CS is high, data ready pulses will be provided
(except
outputting data ready pulses). The DR pin can be used
as an interrupt when connected to an external micro-
controller. When the ARESET pin is low, the DR pin is
not active.
B.5.9.1
To ensure that both channel ADC data are present at
the same time for SPI read, regardless of phase delay
settings for either or both channels, there are two sets
of latches in series with both the data ready and the
‘read start’ triggers.
The first set of latches holds each output when data is
ready and latches both outputs together when
DRMODE<1:0> = 00. When this mode is on, both
ADCs work together and produce one set of available
data after each data ready pulse (that corresponds to
the lagging ADC data ready). The second set of latches
ensures that when reading starts on an ADC output, the
corresponding data is latched so that no data
corruption can occur.
If an ADC read has started, in order to read the
following ADC output, the current reading needs to be
completed (all bits must be read from the ADC output
data registers).
DS39979A-page 454
when
DATA READY PIN (DR)
Data Ready Latches And Data
Ready Modes (DRMODE<1:0>)
the
configuration
prevents
DD
from
Preliminary
) in
B.5.9.2
There are four modes that control the data ready
pulses
DRMODE<1:0> bits in the STATUS/COM register. For
power metering applications, DRMODE<1:0> = 00 is
recommended (Default mode).
The position of DR pulses vary with respect to this
mode, to the OSR and to the PHASE settings:
• DRMODE<1:0> = 11: Both Data Ready pulses
• DRMODE<1:0> = 10: Data Ready pulses from
• DRMODE<1:0> = 01: Data Ready pulses from
• DRMODE<1:0> = 00: (Recommended and
B.5.9.3
There will be no DR pulses if DRMODE<1:0> = 00
when either one or both of the ADCs are in Reset or
Shutdown. In Mode 00, a DR pulse only happens when
both ADCs are ready. Any DR pulse will correspond to
one data on both ADCs. The two ADCs are linked
together and act as if there was only one channel with
the combined data of both ADCs. This mode is very
practical when both ADC channel data retrieval and
processing need to be synchronized, as in power
metering applications.
Figure B-13 represents the behavior of the Data Ready
pin with the different DRMODE and DR_LTY
configurations, while shutdown or Resets are applied.
from ADC Channel 0 and ADC Channel 1 are
output on the DR pin.
ADC Channel 1 are output on the DR pin. DR
pulses from ADC Channel 0 are not present on
the pin.
ADC Channel 0 are output on the DR pin. DR
pulses from ADC Channel 1 are not present on
the pin.
Default mode). Data Ready pulses from the
lagging ADC, between the two, are output on the
DR pin. The lagging ADC depends on the PHASE
register and on the OSR. In this mode, the two
ADCs are linked together so their data is latched
together when the lagging ADC output is ready.
Note:
and
If DRMODE<1:0> = 11, the user will still
be able to retrieve the DR pulse for the
ADC not in shutdown or Reset (i.e., only
one ADC channel needs to be awake).
Data Ready Pin (DR) Control Using
DRMODE Bits
DR Pulses with Shutdown or Reset
Conditions
these
modes
 2010 Microchip Technology Inc.
are
set
with
the