PIC18F87J72-I/PT Microchip Technology, PIC18F87J72-I/PT Datasheet - Page 288

• Manufacturer Part Number: PIC18F87J72-I/PT
• Description: IC PIC MCU 8BIT 14KB FLSH 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F87J72-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 80-TQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: SPI, USART, SPI, I2C
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 14
• Controller Family/series: PIC18F
• No. Of I/o's: 51
• Ram Memory Size: 3923Byte
• Cpu Speed: 48MHz
• No. Of Timers: 4
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F87J72 FAMILY
22.4.2
The AFE uses its own dedicated Serial Peripheral
Interface (SPI) to both send output data from its A/D
Converters, and send and receive control information.
The interface allows the AFE to operate directly with
other microcontrollers and analog peripherals that use
SPI on a common serial bus.
To use the interface, the following connections are
required between the AFE and the MSSP module:
• from SDO (RC5) to SDIA
• from SDI (RC4) to SDOA
• from SCK (RC3) to SCKA
In addition, the AFE requires a chip select signal on the
CSA pin (active-low) to function properly. The chip
select signal can be supplied by any available I/O pin.
22.4.3
In addition to the SPI connections, the AFE requires
three other digital signals for proper control:
• the Data Ready (DR) output, asserted low to
• a module Reset (ARESET), asserted low to inde-
• a clock for the AFE’s digital circuits, supplied on
To use the Data Ready, tie the DR pin to an external
interrupt pin, such as INT0. Asserting DR will cause an
interrupt, the ISR for which can be used to read the
AFE’s data through the SPI. Note that whatever inter-
rupt trigger is used, it must be properly configured to
trigger when the pin is asserted low.
For the Reset input, use an available I/O pin to drive
ARESET low when needed.
For the AFE clock signal, any suitable clock signal in
the proper frequency range (1 MHz to 5 MHz) can be
used. One convenient and low pin count method is to
use a CCP module in PWM mode to generate an
appropriate clock, then connect the module’s output pin
to CLKIA.
22.4.4
The analog signals to be converted to digital values are
connected to the pins of CH0 and/or CH1. Each chan-
nel has inverting and non-inverting inputs (CHn- and
CHn+, respectively), and is fully differential. Limits and
absolute maximums for the inputs are described in
Section 29.0 “Electrical Characteristics”.
DS39979A-page 288
signal that a conversion has been completed and
is ready to be transferred;
pendently force the AFE into a POR event; and
the CLKIA pin.
SERIAL INTERFACE
CONNECTIONS
OTHER INTERFACE
CONNECTIONS
ANALOG INPUTS
Preliminary
The REFIN+/OUT and REFIN- pins are used to supply
an external voltage reference to the AFE; the
REFIN+/OUT pin can also be configured to provide
voltage generated by the AFE’s internal voltage refer-
ence. If the internal voltage reference is enabled,
bypass capacitors to analog ground are recommended
for the REFIN+/OUT pin. The REFIN- pin should be
directly connected to analog ground (as shown in
Figure 22-3).
22.5
To configure the AFE and read A/D conversion data,
follow this sequence:
1.
2.
3.
4.
5.
6.
Note that SPI operations to read or write the AFE’s reg-
isters can be performed even without providing CLKIA
to the AFE. The CLKIA signal is required to perform
A/D conversions and make the Data Ready (DR) signal
available after conversions are done.
Note:
Initialize the MSSP module:
a)
b)
Reset the AFE by pulling ARESET low.
Pull CSA high.
Disable the chip select signals of all the devices
connected to the same SPI bus.
Pull CSA low, then write the register address
with command (read or write selection) to the
AFE through the SPI.
As long as CSA is enabled, the address will
increment automatically after each SPI transfer
is completed. After sending the address and
command, the registers of the AFE can be
written or read.
Disable CSA after read or write to a set of AFE
registers.
When the DR signal is asserted, signalling that
an A/D conversion is complete, use an interrupt
routine to read the data from one or both chan-
nels. The overall method is similar to that for
reading other AFE registers over the SPI,
described in step 5.
Using the AFE
Configure for SPI Master mode, in either
SPI mode 0,0 (CKP = 0, CKE = 1) or mode
1,1 (CKP = 1, CKE = 0).
Configure TRISC for SCK and SDO as out-
puts, and SDI as input.
The first byte sent to the AFE upon
initialization must always be a control byte.
See Appendix B.5 “Serial Interface
Description” for more information.
 2010 Microchip Technology Inc.