FSBB15CH60C Fairchild Semiconductor, FSBB15CH60C Datasheet - Page 10

• Manufacturer Part Number: FSBB15CH60C
• Description: IC POWER MOD SPM 600V SPM27CC
• Manufacturer: Fairchild Semiconductor
• Series: SPM™r
• Type: IGBTr

Specifications of FSBB15CH60C

• Configuration: 3 Phase
• Current: 15A
• Voltage: 600V
• Voltage - Isolation: 2500Vrms
• Package / Case: SPM27CC
• Transistor Polarity: N Channel
• Dc Collector Current: 15A
• Collector Emitter Voltage Vces: 2V
• Power Dissipation Pd: 55W
• Collector Emitter Voltage V(br)ceo: 600V
• Operating Temperature Range: -40°C To
• Operating Temperature (max): 150C
• Operating Temperature (min): -40C
• Pin Count: 27
• Mounting: Through Hole
• Case Length: 44mm
• Case Height: 5.5mm
• Screening Level: Automotive
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FSBB15CH60C Rev. D
Time Charts of SPMs Protective Function
a1 : Control supply voltage rises: After the voltage rises UV
a2 : Normal operation: IGBT ON and carrying current.
a3 : Under voltage detection (UV
a4 : IGBT OFF in spite of control input condition.
a5 : Fault output operation starts.
a6 : Under voltage reset (UV
a7 : Normal operation: IGBT ON and carrying current.
b1 : Control supply voltage rises: After the voltage reaches UV
b2 : Normal operation: IGBT ON and carrying current.
b3 : Under voltage detection (UV
b4 : IGBT OFF in spite of control input condition, but there is no fault output signal.
b5 : Under voltage reset (UV
b6 : Normal operation: IGBT ON and carrying current
Fault Output Signal
Fault Output Signal
Supply Voltage
Supply Voltage
Output Current
Output Current
Circuit State
Circuit State
Input Signal
Input Signal
Protection
Protection
Control
Control
CCR
BSR
)
).
CCD
BSD
Figure 9. Under-Voltage Protection (High-side)
Figure 8. Under-Voltage Protection (Low-side)
).
).
UV
UV
BSR
CCR
High-level (no fault output)
RESET
RESET
a1
b1
CCR
a2
b2
UV
UV
BSR
, the circuits start to operate when next input is applied.
BSD
CCD
10
, the circuits start to operate when next input is applied.
SET
SET
b4
a3
a4
b3
a5
RESET
RESET
a6
b5
a7
b6
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