FSBB20CH60F Fairchild Semiconductor, FSBB20CH60F Datasheet - Page 11

• Manufacturer Part Number: FSBB20CH60F
• Description: IC SMART POWER MOD 20A SPM27-CA
• Manufacturer: Fairchild Semiconductor
• Series: SPM™r
• Type: IGBTr

Specifications of FSBB20CH60F

• Configuration: 3 Phase
• Current: 20A
• Voltage: 600V
• Voltage - Isolation: 2500Vrms
• Package / Case: SPM27CA
• Collector-emitter Saturation Voltage: 2.3 V
• Gate-emitter Leakage Current: 250 uA
• Power Dissipation: 61 W
• Mounting Style: SMD/SMT
• Output Current: 40A
• Supply Voltage Range: 13.5V To 16.5V
• No. Of Pins: 27
• Termination Type: Screw
• Supply Voltage Min: 300V
• Output Current Max: 5mA
• Frequency: 20kHz
• Power Supply Type: Power Module
• Rohs Compliant: Yes
• Filter Terminals: Screw
• Output Voltage Max: 4.5V
• For Use With: FEB154 - BOARD EVAL FOR FSBB20CH60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FSBB20CH60F Rev. D
Note:
1. RC coupling at each input (parts shown dotted) might change depending on the PWM control scheme used in the application and the wiring impedance of the application’s
2. The logic input is compatible with standard CMOS or LSTTL outputs.
Note:
1. It would be recommended that the bootstrap diode, D
2. The bootstrap resistor (R
3. The ceramic capacitor placed between V
high-side.
printed circuit board. The SPM input signal section integrates 3.3k Ω( typ.) pull-down resistor. Therefore, when using an external filtering resistor, please pay attention to the sig-
nal voltage drop at input terminal.
CPU
15V-Line
Figure 10. Recommended Bootstrap Operation Circuit and Parameters
BS
) should be 3 times greater than R
These Values depend on PWM Control Algorithm
R
BS
CC
Figure 9. Recommended CPU I/O Interface Circuit
1000u
-COM should be over 1 µ F and mounted as close to the pins of the SPM as possible.
1nF
22uF
F
D
BS
100
BS
Ω
, has soft and fast recovery characteristics.
0.1uF
E(H)
4.7k
R
C
. The recommended value of R
1nF
PF
1uF
PF
=
Ω
=
5V-Line
11
One-Leg Diagram of SPM
IN
COM
IN
COM
Vcc
Vcc
R
E(H)
OUT
E(H)
HO
VB
VS
V
SL
is 5.6 Ω , but it can be increased up to 20 Ω (maximum) for a slower dv/dt of
CO M
IN
V
IN
FO
P
N
(UH)
(UL)
Inverter
,
,
Output
IN
IN
(VH)
(VL)
SPM
,
,
IN
IN
(W H)
(W L)
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