MFRC52301HN1,157 NXP Semiconductors, MFRC52301HN1,157 Datasheet - Page 41

• Manufacturer Part Number: MFRC52301HN1,157
• Description: IC READER 13.56MHZ 32-HVQFN
• Manufacturer: NXP Semiconductors

Specifications of MFRC52301HN1,157

• Frequency: 13.56MHz
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Rf Type: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935282956157

NXP Semiconductors
MFRC523_34
Product data sheet
PUBLIC
9.2.1.10 FIFOLevelReg register
9.2.1.9 FIFODataReg register
Table 37.
Input and output of 64 byte FIFO buffer.
Table 38.
Table 39.
Indicates the number of bytes stored in the FIFO.
Table 40.
Table 41.
Bit
2 to 0
Bit
Symbol
Access
Bit
7 to 0
Bit
Symbol
Access
Bit
7
6 to 0 FIFOLevel[6:0]
Symbol
FlushBuffer
Symbol
ModemState[2:0]
FlushBuffer
Symbol
FIFOData[7:0] data input and output port for the internal 64-byte FIFO buffer. FIFO
Status2Reg register bit descriptions
FIFODataReg register (address 09h); reset value: xxh bit allocation
FIFODataReg register bit descriptions
FIFOLevelReg register (address 0Ah); reset value: 00h bit allocation
FIFOLevelReg register bit descriptions
7
W
7
All information provided in this document is subject to legal disclaimers.
Rev. 3.5 — 24 September 2010
Value Description
1
-
6
Description
buffer acts as parallel in/parallel out converter for all serial data stream
inputs and outputs
6
Value
-
000
001
010
011
100
101
110
immediately clears the internal FIFO buffer’s read and write
pointer and ErrorReg register’s BufferOvfl bit. Reading this bit
always returns 0
indicates the number of bytes stored in the FIFO buffer. Writing to
the FIFODataReg register increments and reading decrements
the FIFOLevel value
115235
5
Description
shows the state of the transmitter and receiver state
machines:
5
idle
wait for the BitFramingReg register’s StartSend bit
TxWait: wait until RF field is present if the TModeReg
register’s TxWaitRF bit is set to logic 1. The minimum
time for TxWait is defined by the TxWaitReg register
transmitting
RxWait: wait until RF field is present if the TModeReg
register’s TxWaitRF bit is set to logic 1. The minimum
time for RxWait is defined by the RxWaitReg register
wait for data
receiving
FIFOData[7:0]
4
4
…continued
D
FIFOLevel[6:0]
3
R
3
2
2
Contactless reader IC
MFRC523
© NXP B.V. 2010. All rights reserved.
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