MFRC52301HN1,157 NXP Semiconductors, MFRC52301HN1,157 Datasheet - Page 29

• Manufacturer Part Number: MFRC52301HN1,157
• Description: IC READER 13.56MHZ 32-HVQFN
• Manufacturer: NXP Semiconductors

Specifications of MFRC52301HN1,157

• Frequency: 13.56MHz
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Rf Type: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935282956157

NXP Semiconductors
MFRC523_34
Product data sheet
PUBLIC
8.7 Timer unit
The ComIrqReg register’s ErrIRq bit indicates an error detected by the contactless UART
during send or receive. This is indicated when any bit is set to logic 1 in register ErrorReg.
Table 19.
The MFRC523A has a timer unit which the external host can use to manage timing tasks.
The timer unit can be used in one of the following timer/counter configurations:
The timer unit can be used to measure the time interval between two events or to indicate
that a specific event occurred after a specific time. The timer can be triggered by events
explained in the paragraphs below. The timer does not influence any internal events, for
example, a time-out during data reception does not automatically influence the reception
process. In addition, several timer-related bits can be used to generate an interrupt.
The timer has an input clock of 13.56 MHz derived from the 27.12 MHz quartz crystal
oscillator. The timer consists of two stages: prescaler and counter.
The prescaler (TPrescaler) is a 12-bit counter. The reload values (TReloadVal_Hi[7:0] and
TReloadVal_Lo[7:0]) for TPrescaler can be set between 0 and 4095 in the TModeReg
register’s TPrescaler_Hi[3:0] bits and TPrescalerReg register’s TPrescaler_Lo[7:0] bits.
The reload value for the counter is defined by 16 bits between 0 and 65535 in the
TReloadReg register.
The current value of the timer is indicated in the TCounterValReg register.
When the counter reaches 0, an interrupt is automatically generated, indicated by the
ComIrqReg register’s TimerIRq bit setting. If enabled, this event can be indicated on
pin IRQ. The TimerIRq bit can be set and reset by the host. Depending on the
configuration, the timer will stop at 0 or restart with the value set in the TReloadReg
register.
The timer status is indicated by the Status1Reg register’s TRunning bit.
Interrupt flag
TimerIRq
TxIRq
CRCIRq
RxIRq
IdleIRq
HiAlertIRq
LoAlertIRq
ErrIRq
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•
•
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Timeout counter
Watchdog counter
Stop watch
Programmable one shot
Periodic trigger
Interrupt sources
Interrupt source
timer unit
transmitter
CRC coprocessor
receiver
ComIrqReg register
FIFO buffer
FIFO buffer
contactless UART
All information provided in this document is subject to legal disclaimers.
Rev. 3.5 — 24 September 2010
115235
Trigger action
the timer counts from 1 to 0
a transmitted data stream ends
all data from the FIFO buffer has been processed
a received data stream ends
command execution finishes
the FIFO buffer is almost full
an error is detected
the FIFO buffer is almost empty
Contactless reader IC
MFRC523
© NXP B.V. 2010. All rights reserved.
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