MFRC523 NXP Semiconductors, MFRC523 Datasheet

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... The MFRC523 is a highly integrated reader/writer for contactless communication at 13.56 MHz. The MFRC523 reader supports ISO/IEC 14443 A/MIFARE mode. The MFRC523’s internal transmitter is able to drive a reader/writer antenna designed to communicate with ISO/IEC 14443 A/MIFARE cards and transponders without additional active circuitry. The receiver module provides a robust and efficient implementation for demodulating and decoding signals from ISO/IEC 14443 A/MIFARE compatible cards and transponders ...

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... SS(TVSS DDA DDD DD(TVDD) DD(PVDD) hard power-down; pin NRSTPD set LOW soft power-down; RF level detector on pin DVDD DDD All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 115233 MFRC523 Contactless reader IC Min Typ [1][2] ; 2.5 3 2.5 3.3 2.5 3.3 [3] 1.6 1 ...

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... CommandReg register’s RcvOff bit = 1 pin PVDD pin TVDD; continuous wave HVQFN32 . DDD Description 32 terminal; body 5 × 5 × 0. terminal; body 5 × 5 × 0.85 mm All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 115233 MFRC523 Contactless reader IC Min Typ - DDA [5] - ...

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... Various host interfaces are implemented to meet different customer requirements. Fig 1. MFRC523_33 Product data sheet PUBLIC ANALOG CONTACTLESS ANTENNA INTERFACE UART Simplified block diagram of the MFRC523 All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 115233 MFRC523 Contactless reader IC REGISTER BANK FIFO SERIAL UART BUFFER ...

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... RATING REFERENCE VOLTAGE ANALOG TEST I-CHANNEL MULTIPLEXOR AMPLIFIER AND DIGITAL TO I-CHANNEL ANALOG DEMODULATOR CONVERTER VMID AUX1 AUX2 Fig 2. Detailed block diagram of the MFRC523 MFRC523_33 Product data sheet PUBLIC D6/ADR_0/ D2/ADR_4 D4/ADR_2 MOSI/MX D5/ADR_1/ D7/SCL/ D3/ADR_3 SCK/DTRQ MISO/ ...

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... MHz energy carrier output transmitter output stage 2 ground analog power supply All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 115233 MFRC523 Contactless reader IC 24 SDA/NSS/RX 23 IRQ 22 ...

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... SPI master in, slave out UART data output to microcontroller external address input for coding I Section 8.3 “Digital interfaces”. All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 115233 MFRC523 Contactless reader IC [2] [2] [2] 2 [2] C-bus address © NXP B.V. 2010. All rights reserved. ...

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... The MFRC523’s contactless UART and dedicated external host must manage the complete ISO/IEC 14443 A/MIFARE protocol. framing according to ISO/IEC 14443 A/MIFARE. MFRC523_33 Product data sheet PUBLIC BATTERY MFRC523 ...

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... The MFRC523 supports direct interfacing of hosts using SPI, I interfaces. The MFRC523 resets its interface and checks the current host interface type automatically after performing a power-on or hard reset. The MFRC523 identifies the host interface by sensing the logic levels on the control pins after the reset phase. This is done using a combination of fixed pin connections ...

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... Data bytes on both MOSI and MISO lines are sent with the MSB first. Data on both MOSI and MISO lines must be stable on the rising edge of the clock and can be changed on the falling edge. Data is provided by the MFRC523 on the falling clock edge and is stable during the rising clock edge. ...

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... The address byte must meet the following format. The MSB of the first byte defines the mode used. To read data from the MFRC523 the MSB is set to logic 1. To write data to the MFRC523 the MSB must be set to logic 0. Bits define the address and the LSB is set to logic 0. ...

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... Table 10 6 × 27.12 10 ------------------------------- - = ( ) BR_T0 + 1 All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 115233 MFRC523 Contactless reader IC Table 9. Examples of different Table 10. Bit 3 Bit 4 Bit 5 Bit Transfer speed accuracy (%) −0.25 0.32 −0.25 0.32 0.32 −0.25 −0.25 − ...

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... UART framing Length 1-bit 8 bits 1-bit Read data byte order Byte 0 address - All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 115233 MFRC523 Contactless reader IC Value 0 data 1 Table 12 must be Byte 1 - data 0 © NXP B.V. 2010. All rights reserved ...

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... DTRQ (1) Reserved. Fig 9. UART read data timing diagram Write data: To write data to the MFRC523 using the UART interface, the structure shown in Table 13 The first byte sent defines both the mode and the address. Table 13. Pin RX (pin 24) TX (pin 31) ...

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... Address byte: The address byte has to meet the following format: The MSB of the first byte sets the mode used. To read data from the MFRC523, the MSB is set to logic 1. To write data to the MFRC523 the MSB is set to logic 0. Bit 6 is reserved for future use, and bits define the address; see ...

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... Slave mode. Therefore the MFRC523 does not implement clock generation or access arbitration. Fig 11. I The MFRC523 can act either as a slave receiver or slave transmitter in Standard mode, Fast mode and High-speed mode. SDA is a bidirectional line connected to a positive supply voltage using a current source or a pull-up resistor ...

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... C-bus, unique START (S) and STOP (P) conditions S START condition 16. The number of transmitted bytes during one data transfer is unrestricted All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 115233 MFRC523 Contactless reader IC change of data allowed mbc621 P STOP condition © NXP B.V. 2010. All rights reserved. ...

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... LOW while interrupts are serviced ACK C-bus All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 115233 MFRC523 Contactless reader IC not acknowledge acknowledge 2 8 clock pulse for acknowledgement acknowledgement signal from receiver 1 ...

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... EA. If pin EA is set LOW, the upper 4 bits of the device bus address are reserved by NXP Semiconductors and set to 0101b for all MFRC523 devices. The remaining 3 bits (ADR_0, ADR_1, ADR_2) of the slave address can be freely configured by the customer to prevent collisions with other I ...

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... NXP Semiconductors 8.3.4.7 Register read access To read out data from a specific register address in the MFRC523, the host controller must use the following procedure: • Firstly, a write access to the specific register address must be performed as indicated in the frame that follows • The first byte of a frame indicates the device address according to the I • ...

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... When HS mode starts, the active master sends a repeated START condition (Sr) followed by a 7-bit slave address with a R/W bit address and receives an acknowledge bit (A) from the selected MFRC523. Data transfer continues in HS mode after the next repeated START (Sr), only switching back to F/S mode after a STOP condition (P). To reduce the overhead of the master code, a master links a number of HS mode transfers, separated by repeated START conditions (Sr) ...

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... F/S mode R/W A 7-bit SLA mode All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 115233 MFRC523 Contactless reader (8-bit data + A/ ...

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... NXP Semiconductors 8.3.4.11 Switching between F/S mode and HS mode After reset and initialization, the MFRC523 is in Fast mode (which is in effect F/S mode as Fast mode is downward-compatible with Standard mode). The connected MFRC523 recognizes the “S 00001XXX A” sequence and switches its internal circuitry from the Fast mode setting to the HS mode setting ...

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... [ RF_n pCW All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 115233 MFRC523 Contactless reader IC 79. The signal on pins TX1 Section 9.2.2.5 on GSPMos GSNMos Remarks [1] [ not specified switched off pMod nMod ...

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... [1] [ [1] [ All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 115233 MFRC523 Contactless reader IC GSPMos GSNMos Remarks TX2 [1] [1] [ not specified switched off RF pMod nMod - RF pCW nCW RF_n ...

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... It is possible for the interface between these two blocks to be configured so that the interfacing signals are routed to pins MFIN and MFOUT. This topology allows the analog block of the MFRC523 to be connected to the digital block of another device. The serial signal switch is controlled by the TxSelReg and RxSelReg registers. ...

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... Fig 21. Overview of MFIN and MFOUT signal routing MFOUT 3-state 0 3-state LOW 1 internal envelope MFOutSel[3:0] HIGH 2 envelope from pin MFIN test bus 3 internal envelope 4 5 reserved 6 7 SUBCARRIER DEMODULATOR MFIN 0 TX2 MODULATOR DRIVER 1 TX1 2 DRIVER HIGH 3 Sel[1:0] ANALOG MODULE MFRC523 DEMODULATOR RX 001aal161 ...

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... CRC preset value 8.5 FIFO buffer An 8 × 64 bit FIFO buffer is used in the MFRC523. It buffers the input and output data stream between the host and the MFRC523’s internal state machine. This makes it possible to manage data streams bytes long without the need to take timing constraints into account ...

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... LoAlert 8.6 Interrupt request system The MFRC523 indicates certain events by setting the Status1Reg register’s IRq bit and, if activated, by pin IRQ. The signal on pin IRQ can be used to interrupt the host using its interrupt handling capabilities. This allows the implementation of efficient host software. ...

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... CRCIRq RxIRq IdleIRq HiAlertIRq LoAlertIRq ErrIRq 8.7 Timer unit The MFRC523A has a timer unit which the external host can use to manage timing tasks. The timer unit can be used in one of the following timer/counter configurations: • Timeout counter • Watchdog counter • Stop watch • ...

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... TReloadVal 13.56 MHz ( × ) × 4095 65535 + 1 = ---------------------------------------------------------------------- - 13.56 MHz All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 115233 MFRC523 Contactless reader shown in Equation 6, where the d © NXP B.V. 2010. All rights reserved (5) ( ...

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... AVDD and it will take a certain time (t cycles can be detected by the internal logic recommended for the serial UART, to first send the value 55h to the MFRC523. The oscillator must be stable for further access to the registers. To ensure this, perform a read access to address 0 until the MFRC523 answers to the last read command with the register content of address 0 ...

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... The spike filter rejects signals shorter than 10 ns. In order to perform a reset, the signal must be LOW for at least 100 ns. 8.10.2 Oscillator start-up time If the MFRC523 has been set to a Power-down mode or is powered start-up time for the MFRC523 depends on the oscillator used and is shown in The time (t start-up time is defined by the crystal ...

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... NXP Semiconductors 9. MFRC523 registers 9.1 Register bit behavior Depending on the functionality of a register, the access conditions to the register can vary. In principle, bits with same behavior are grouped in common registers. The access conditions are described in Table 19. Abbreviation Behavior R reserved RFT Table 20. ...

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... NXP Semiconductors Table 20. MFRC523 register overview Address Register name (hex) 0Dh BitFramingReg 0Eh CollReg 0Fh Reserved Page 1: Command 10h Reserved 11h ModeReg 12h TxModeReg 13h RxModeReg 14h TxControlReg 15h TxASKReg 16h TxSelReg 17h RxSelReg 18h RxThresholdReg 19h DemodReg 1Ah Reserved 1Bh ...

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... NXP Semiconductors Table 20. MFRC523 register overview Address Register name (hex) 2Eh TCounterValReg 2Fh Page 3: Test register 30h Reserved 31h TestSel1Reg 32h TestSel2Reg 33h TestPinEnReg 34h TestPinValueReg 35h TestBusReg 36h AutoTestReg 37h VersionReg 38h AnalogTestReg 39h TestDAC1Reg 3Ah TestDAC2Reg 3Bh TestADCReg 3Ch to 3Fh Reserved ...

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... Soft Power-down mode entered 0 MFRC523 starts the wake up procedure during which this bit is read as a logic read as a logic 0 when the MFRC523 is ready; see Section 8.8.2 on page 32 Remark: The PowerDown bit cannot be set when the SoftReset command is activated activates a command based on the Command value ...

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... ComIrqReg register (address 04h); reset value: 14h bit allocation Set1 TxIRq RxIRq IdleIRq All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 115233 MFRC523 Contactless reader reserved CRCIEn R HiAlertIRq LoAlertIRq ErrIRq ...

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... CalcCRC command is active and all data is processed - reserved for future use All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 115233 MFRC523 Contactless reader IC Table 149 reserved CRCIRq reserved - D - © ...

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... MFRC523’s internal state machine (e.g. receiver) tries to write data to the FIFO buffer even though it is already full 1 a bit-collision is detected cleared automatically at receiver start-up phase ...

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... ComIEnReg and DivIEnReg registers 1 MFRC523’s timer unit is running, i.e. the timer will decrement the TCounterValReg register with the next timer clock Remark: in gated mode, the TRunning bit is set to logic 1 when the timer is enabled by TModeReg register’s TGated[1:0] bits; this bit is not ...

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... TxWaitRF bit is set to logic 1 the minimum time for RxWait is defined by the RxWaitReg register 101 wait for data 110 receiving All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 115233 MFRC523 Contactless reader reserved MFCrypto1On ModemState[2:0] - ...

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... FIFODataReg register increments and reading decrements the FIFOLevel value WaterLevelReg register (address 0Bh); reset value: 08h bit allocation reserved - All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 115233 MFRC523 Contactless reader FIFOData[7: FIFOLevel[6:0] ...

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... All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 115233 MFRC523 Contactless reader IC 41 reserved RxLastBits[2:0] - © ...

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... CollPos[4:0] All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 115233 MFRC523 Contactless reader reserved TxLastBits[2:0] - R/W 5 ...

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... Reserved register bit descriptions Symbol Description reserved reserved for future use All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 115233 MFRC523 Contactless reader IC …continued nd indicates a bit-collision in the 32 st indicates a bit-collision in the 1 bit th indicates a bit-collision in the 8 bit ...

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... A671h 11 FFFFh TxModeReg register (address 12h); reset value: 00h bit allocation TxCRCEn TxSpeed[2:0] R/W D All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 115233 MFRC523 Contactless reader PolMFin reserved CRCPreset[1: InvMod TxFraming ...

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... Description RxCRCEn 1 enables the CRC calculation during reception Remark: can only be set to logic 0 at 106 kBd RxSpeed[2:0] defines the bit rate while receiving data the MFRC523 handles transfer speeds up to 848 kBd 000 106 kBd 001 212 kBd 010 424 kBd ...

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... TX2 delivers the 13.56 MHz energy carrier modulated by the transmission data 1 output signal on pin TX1 delivers the 13.56 MHz energy carrier modulated by the transmission data All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 115233 MFRC523 Contactless reader IC …continued InvTx1RF Tx2CW reserved Tx2RFEn Tx1RFEn ...

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... Miller pulse encoded 10 modulation signal (envelope) from pin MFIN 11 HIGH; the HIGH level depends on the setting of bits InvTx1RFOn/InvTx1RFOff and InvTx2RFOn/InvTx2RFOff All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 115233 MFRC523 Contactless reader reserved - ...

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... Receive command all other commands, such as Transceive, MFAuthent use this parameter the counter starts immediately after the external RF field is switched on All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 115233 MFRC523 Contactless reader IC …continued RxWait[5:0] R/W © ...

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... PLL during data reception [1:0] Remark: if set to 00b the PLL is frozen during data reception TauSync - changes the time constant of the internal PLL during burst [1:0] All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 115233 MFRC523 Contactless reader reserved CollLevel[2: ...

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... Description reserved reserved for future use TxWait defines the additional response time 7 bits are added to the value of the register bit by default All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 115233 MFRC523 Contactless reader reserved - ...

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... NoTxEOF 1 EOF is suppressed TxEGT defines EGT bit length 00 no bits 01 1 bit 10 2 bits 11 3 bits All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 115233 MFRC523 Contactless reader reserved R NoTxSOF NoTxEOF Width R/W R/W R/W © NXP B.V. 2010. All rights reserved. ...

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... BR_T0 adjusts the transfer speed: for description, see Section 8.3.3.2 on page 12 BR_T1[4:0] factor BR_T1 adjusts the transfer speed: for description, see Section 8.3.3.2 on page 12 All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 115233 MFRC523 Contactless reader BR_T1[4:0] R/W © ...

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... Symbol Description CRCResultLSB shows the value of the least significant byte of the CRCResultReg [7:0] register only valid if Status1Reg register’s CRCReady bit is set to logic 1 All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 115233 MFRC523 Contactless reader reserved 4 3 ...

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... Reserved register (address 25h); reset value: 87h bit allocation Reserved register bit descriptions Symbol Description reserved reserved for future use All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 115233 MFRC523 Contactless reader reserved - ModWidth[7:0] R/W ...

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... Remark: the conductance value is binary weighted during soft Power-down mode the highest bit is forced to logic 1 value is only used if driver TX1 or TX2 is switched on All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 115233 MFRC523 Contactless reader reserved ...

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... Power-down mode the highest bit is forced to logic 1 if the TxASKReg register’s Force100ASK bit is set to logic 1 the value of ModGsP has no effect TAuto TGated[1:0] TAutoRestart R/W R/W All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 115233 MFRC523 Contactless reader CWGsP[5:0] R ModGsP[5:0] R ...

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... MHz and TPreScaler = [TPrescaler_Hi:TPrescaler_Lo] (TPrescaler value on 12 bits); for detailed description, see “Timer unit” All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 115233 MFRC523 Contactless reader IC 6 × 13. -------------------------------------- - TPrescaler + ...

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... All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 115233 MFRC523 Contactless reader IC : timer 6 × Section 8.7 “Timer unit” ...

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... TstBusBitSel selects a test bus signal which is output at pin MFOUT [2:0] if AnalogSelAux2[3:0] = FFh in AnalogTestReg register, test bus signal is also output at pins AUX1 or AUX2 All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 115233 MFRC523 Contactless reader ...

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... Remark: If the SPI is used, only pins can be used. If the serial UART interface is used and the RS232LineEn bit is set to logic 1 only pins can be used. - reserved for future use All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 115233 MFRC523 Contactless reader TestBusSel[4:0] R/W Section 16.1 “ ...

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... TestSel2Reg register; see Section 16.1 on page reserved AmpRcv RFT - R/W - All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 115233 MFRC523 Contactless reader TestPinValue[5:0] R TestBus[7: ...

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... Remark: for default operation the self test must be disabled by 0000b Symbol Description Version[7:0] indicates current software version of the MFRC523 Remark: the current version of the MFRC523 is 90h or 91h AnalogSelAux1[3:0] R/W All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 ...

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... TstBusBitSel[2:0] bits Remark: all test signals are described in page 80 - controls pin AUX2 (see bit descriptions for AUX1) All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 115233 MFRC523 Contactless reader IC [1] [1] [1] [1] [1] Section 16.1 on © NXP B.V. 2010. All rights reserved. ...

Page 67

... DAC2 can be routed to AUX2 by setting value AnalogSelAux2[3:0] to 0001b in the AnalogTestReg register ADC_I[3:0] R Symbol Description ADC_I[3:0] ADC I channel value ADC_Q[3:0] ADC Q channel value All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 115233 MFRC523 Contactless reader TestDAC1[5:0] R TestDAC2[5:0] R ...

Page 68

... Table 148. Reserved register bit descriptions Bit 10. MFRC523 command set The MFRC523 operation is determined by a state machine capable of performing a set of commands. A command is executed by writing a command code (see CommandReg register. Arguments and/or data necessary to process a command are exchanged via the FIFO buffer ...

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... NXP Semiconductors 10.1 General description The MFRC523 operation is determined by a state machine capable of performing a set of commands. A command is executed by writing a command code (see CommandReg register. Arguments and/or data necessary to process a command are exchanged via the FIFO buffer. 10.2 General behavior • Each command that needs a data bit stream (or data byte stream input immediately processes any data in the FIFO buffer ...

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... CommandReg register Command[3:0] bits, for example, the RcvOff bit or the PowerDown bit. 10.3.1.7 Receive The MFRC523 activates the receiver path and waits for a data stream to be received. The correct settings must be chosen before starting this command. MFRC523_33 ...

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... This command automatically terminates when the MIFARE card is authenticated and the Status2Reg register’s MFCrypto1On bit is set to logic 1. MFRC523_33 Product data sheet PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 115233 MFRC523 Contactless reader IC © NXP B.V. 2010. All rights reserved ...

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... MFIN and RX pin MFIN per package; and V in shortcut DDD mode JESD22-A114-B MM; 0.75 μH, 200 pF; JESD22-A114-A All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 115233 MFRC523 Contactless reader IC Min Max −0.5 +4.0 −0.5 +4.0 −0.5 +4.0 −0.5 +4.0 −0.5 +4.0 − ...

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... SSA SSD SS(PVSS) SS(TVSS) HVQFN32 . DDD Conditions in still air with exposed pin soldered layer JEDEC PCB Conditions All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 115233 MFRC523 Contactless reader IC Min Typ [1][2] ; 2.5 3 [1][2] ; 2.5 3 [1][2] ; 2.5 3 ...

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... DD(SVDD DD(SVDD DD(SVDD DD(SVDD DD(PVDD DD(PVDD) O All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 115233 MFRC523 Contactless reader IC Min Typ Max - 350 - - 100 - - − 0. ...

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... DD(TVDD DD(PVDD) [2] hard power-down; pin NRSTPD set LOW [2] soft power-down; RF level detector on pin DVDD DDD All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 115233 MFRC523 Contactless reader IC Min Typ Max - - − 0 DDD DDD ...

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... RcvOff = 1 [3] pin PVDD [4][5][6] pin TVDD; continuous wave [7] pin SVDD RMS pin OSCOUT pin OSCOUT pin OSCOUT pin OSCIN All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 115233 MFRC523 Contactless reader IC Min Typ Max - ...

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... START condition set-up time for STOP condition LOW period of the SCL clock HIGH period of the SCL clock All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 115233 MFRC523 Contactless reader IC V mod V V i(p-p)(max) i(p-p)(min) ...

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... SU;DAT t t LOW HIGH t HD;STA t HD;DAT S All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 115233 MFRC523 Contactless reader IC Conditions Fast mode Min Max 0 900 100 - SCL signal 20 300 SCL signal 20 300 SDA and SCL 20 300 ...

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... NXP Semiconductors 15. Application information A typical application diagram using a complementary antenna connection to the MFRC523 is shown in The antenna tuning and RF part matching is described in the application note Ref. 2. NRSTPD interface MICRO- PROCESSOR Fig 27. Typical application diagram MFRC523_33 Product data sheet PUBLIC Figure 27. supply DVDD ...

Page 80

... NXP Semiconductors 16. Test information 16.1 Test signals 16.1.1 Self test The MFRC523 has the capability to perform a digital self test. The self test is started by using the following procedure: 1. Perform a soft reset. 2. Clear the internal buffer by writing 25 bytes of 00h and implement the Config command. 3. Enable the self test by writing 09h to the AutoTestReg register. ...

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... 16.1.3 Test signals on pins AUX1 or AUX2 The MFRC523 allows the user to select internal signals for measurement on pins AUX1 or AUX2. These measurements can be helpful during the design-in phase to optimize the design or used for test purposes. Table 158 AnalogSelAux1[3:0] or AnalogSelAux2[3:0] in the AnalogTestReg register. ...

Page 82

... TestDAC1 on pin AUX1 and TestDAC2 on pin AUX2 when the (1) (2) shows test signals Corr1 and MinLevel on pins AUX1 and AUX2, respectively. All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 115233 MFRC523 Contactless reader IC 001aak597 100 ms/div 001aak598 (1) (2) (3) 10 μ ...

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... PUBLIC shows the channel behavior test signals ADC_I and ADC_Q on pins AUX1 and shows the RxActive and TxActive test signals relating to RF communication. All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 115233 MFRC523 Contactless reader IC 001aak599 (1) (2) (3) 5 μ ...

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... Fig 31. Output RxActive on pin AUX1 and TxActive on pin AUX2 MFRC523_33 Product data sheet PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 115233 MFRC523 Contactless reader IC 001aak600 (1) (2) (3) 10 μs/div © NXP B.V. 2010. All rights reserved. ...

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... PUBLIC shows the data stream that is currently being received. The TestSel2Reg 80. The TestSel1Reg register’s TstBusBitSel[2:0] bits are set All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 115233 MFRC523 Contactless reader IC 001aak601 (1) (2) 20 μs/div © NXP B.V. 2010. All rights reserved. ...

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... 5.1 3.25 5.1 3.25 0.5 3.5 4.9 2.95 4.9 2.95 REFERENCES JEDEC JEITA MO-220 - - - All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 115233 MFRC523 Contactless reader detail 0.5 0.05 0.1 3.5 0.1 0.05 0.3 EUROPEAN PROJECTION ...

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... Fig 34. Packing information 1 tray MFRC523_33 Product data sheet PUBLIC strap 46 mm from corner All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 115233 MFRC523 Contactless reader IC tray ESD warning preprinted barcode label (permanent) barcode label (peel-off) QA seal Hyatt patent preprinted ...

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... Fig 35. Packing information 5 trays MFRC523_33 Product data sheet PUBLIC strap 46 mm from corner All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 115233 MFRC523 Contactless reader IC tray ESD warning preprinted barcode label (permanent) barcode label (peel-off) QA seal Hyatt patent preprinted ...

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... Universal Asynchronous Receiver Transmitter ) / ( measured at the card’s coil. min max min All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 115233 MFRC523 Contactless reader IC − max min max min © NXP B.V. 2010. All rights reserved. ...

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... Register and bit names: updated • Register tables: presentation updated • Parameter symbols: updated • Section 9 “MFRC523 registers” now follows Section 8 “Functional description” • Section 16 “Test information” added, incorporating Section 16.1 “Test signals” 115231 May 2007 115230 September 2006 ...

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... NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 115233 MFRC523 Contactless reader IC © NXP B.V. 2010. All rights reserved ...

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... All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 115233 MFRC523 Contactless reader IC This NXP Semiconductors IC is ISO/IEC 14443 Type B software enabled and is licensed under Innovatron’s Contactless Card patents license for ISO/IEC 14443 B. The license includes the right to use the IC in systems and/or end-user equipment. © ...

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... TX2 . . . . . . . . . . . . . . . . . . . . . . .25 Table 17. CRC coprocessor parameters . . . . . . . . . . . . .28 Table 18. Interrupt sources . . . . . . . . . . . . . . . . . . . . . . .30 Table 19. Behavior of register bits and their designation . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Table 20. MFRC523 register overview . . . . . . . . . . . . . .34 Table 21. Reserved register (address 00h); reset value: 00h bit allocation . . . . . . . . . . . . .37 Table 22. Reserved register bit descriptions . . . . . . . . . .37 Table 23. CommandReg register (address 01h); ...

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... Table 133. AnalogTestReg register (address 38h); reset value: 00h bit allocation . . . . . . . . . . . . . 65 Table 134. AnalogTestReg register bit descriptions . . . . . 66 All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 115233 MFRC523 Contactless reader IC continued >> © NXP B.V. 2010. All rights reserved ...

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... Table 157. Test bus signals: TestBusSel[4:0] = 0Dh . . . . .81 Table 158. Test signal descriptions . . . . . . . . . . . . . . . . . .81 Table 159. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .89 Table 160. Revision history . . . . . . . . . . . . . . . . . . . . . . . .90 MFRC523_33 Product data sheet PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 5 March 2010 115233 MFRC523 Contactless reader IC © NXP B.V. 2010. All rights reserved ...

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... Figures Fig 1. Simplified block diagram of the MFRC523 Fig 2. Detailed block diagram of the MFRC523 . . . . . . . .5 Fig 3. Pinning configuration HVQFN32 (SOT617- Fig 4. MFRC523 Read/Write mode . . . . . . . . . . . . . . . . .8 Fig 5. ISO/IEC 14443 A/MIFARE Read/Write mode communication diagram Fig 6. Data coding and framing according to ISO/IEC 14443 Fig 7. SPI connection to host . . . . . . . . . . . . . . . . . . . . .10 Fig 8 ...

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... Hard power-down 8.8.2 Soft Power-down mode . . . . . . . . . . . . . . . . . 32 8.8.3 Transmitter Power-down mode . . . . . . . . . . . 32 8.9 Oscillator circuit . . . . . . . . . . . . . . . . . . . . . . . 32 8.10 Reset and oscillator start-up time . . . . . . . . . 33 8.10.1 Reset timing requirements . . . . . . . . . . . . . . . 33 8.10.2 Oscillator start-up time . . . . . . . . . . . . . . . . . . 33 9 MFRC523 registers . . . . . . . . . . . . . . . . . . . . . 34 9.1 Register bit behavior . . . . . . . . . . . . . . . . . . . 34 9.2 Register descriptions . . . . . . . . . . . . . . . . . . . 37 9.2.1 Page 0: Command and status . . . . . . . . . . . . 37 9.2.1.1 Reserved register 00h . . . . . . . . . . . . . . . . . . 37 9.2.1.2 CommandReg register 9.2.1.3 ComIEnReg register . . . . . . . . . . . . . . . . . . . 37 9.2.1.4 DivIEnReg register ...

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... TestPinEnReg register . . . . . . . . . . . . . . . . . . 63 9.2.4.5 TestPinValueReg register . . . . . . . . . . . . . . . . 63 9.2.4.6 TestBusReg register . . . . . . . . . . . . . . . . . . . . 64 9.2.4.7 AutoTestReg register . . . . . . . . . . . . . . . . . . . 64 9.2.4.8 VersionReg register . . . . . . . . . . . . . . . . . . . . 65 9.2.4.9 AnalogTestReg register . . . . . . . . . . . . . . . . . 65 9.2.4.10 TestDAC1Reg register . . . . . . . . . . . . . . . . . . 67 9.2.4.11 TestDAC2Reg register . . . . . . . . . . . . . . . . . . 67 9.2.4.12 TestADCReg register . . . . . . . . . . . . . . . . . . . 67 9.2.4.13 Reserved register 3Ch . . . . . . . . . . . . . . . . . . 67 10 MFRC523 command set . . . . . . . . . . . . . . . . . 68 10.1 General description . . . . . . . . . . . . . . . . . . . . 69 10.2 General behavior . . . . . . . . . . . . . . . . . . . . . . 69 10.3 MFRC523 command overview . . . . . . . . . . . . 69 10.3.1 MFRC523 command descriptions . . . . . . . . . 69 10.3.1.1 Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 10.3.1.2 Mem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 10.3.1.3 Generate RandomID . . . . . . . . . . . . . . . . . . . 70 10.3.1.4 CalcCRC 10.3.1.5 Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 10.3.1.6 NoCmdChange ...