MFRC52301HN1,157 NXP Semiconductors, MFRC52301HN1,157 Datasheet - Page 27

• Manufacturer Part Number: MFRC52301HN1,157
• Description: IC READER 13.56MHZ 32-HVQFN
• Manufacturer: NXP Semiconductors

Specifications of MFRC52301HN1,157

• Frequency: 13.56MHz
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Rf Type: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935282956157

NXP Semiconductors
MFRC523_34
Product data sheet
PUBLIC
8.4.5 CRC coprocessor
8.5.1 Accessing the FIFO buffer
8.5.2 Controlling the FIFO buffer
8.5.3 FIFO buffer status information
8.5 FIFO buffer
The following CRC coprocessor parameters can be configured:
Table 18.
An 8 × 64 bit FIFO buffer is used in the MFRC523. It buffers the input and output data
stream between the host and the MFRC523’s internal state machine. This makes it
possible to manage data streams up to 64 bytes long without the need to take timing
constraints into account.
The FIFO buffer input and output data bus is connected to the FIFODataReg register.
Writing to this register stores one byte in the FIFO buffer and increments the internal FIFO
buffer write pointer. Reading from this register shows the FIFO buffer contents stored in
the FIFO buffer read pointer and decrements the FIFO buffer read pointer. The distance
between the write and read pointer can be obtained by reading the FIFOLevelReg
register.
When the microcontroller starts a command, the MFRC523 can, while the command is in
progress, access the FIFO buffer according to that command. Only one FIFO buffer has
been implemented which can be used for input and output. The microcontroller must
ensure that there are not any unintentional FIFO buffer accesses.
The FIFO buffer pointers can be reset by setting FIFOLevelReg register’s FlushBuffer bit
to logic 1. Consequently, the FIFOLevel[6:0] bits are all set to logic 0 and the ErrorReg
register’s BufferOvfl bit is cleared. The bytes stored in the FIFO buffer are no longer
accessible allowing the FIFO buffer to be filled with another 64 bytes.
The host can get the following FIFO buffer status information:
Parameter
CRC register length
CRC algorithm
CRC preset value
•
•
•
•
•
•
The CRC preset value can be either 0000h, 6363h, A671h or FFFFh depending on
the ModeReg register’s CRCPreset[1:0] bits setting
The CRC polynomial for the 16-bit CRC is fixed to x
The CRCResultReg register indicates the result of the CRC calculation. This register
is split into two 8-bit registers representing the higher and lower bytes.
The ModeReg register’s MSB first bit indicates that data will be loaded with the MSB
first.
Number of bytes stored in the FIFO buffer: FIFOLevelReg register’s FIFOLevel[6:0]
FIFO buffer almost full warning: Status1Reg register’s HiAlert bit
CRC coprocessor parameters
All information provided in this document is subject to legal disclaimers.
Rev. 3.5 — 24 September 2010
Value
16-bit CRC
algorithm according to ISO/IEC 14443 A and ITU-T
0000h, 6363h, A671h or FFFFh depending on the setting of the
ModeReg register’s CRCPreset[1:0] bits
115235
16
+ x
12
+ x
Contactless reader IC
5
+ 1
MFRC523
© NXP B.V. 2010. All rights reserved.
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