T48C862M-R4-TNQ Atmel, T48C862M-R4-TNQ Datasheet - Page 83

• Manufacturer Part Number: T48C862M-R4-TNQ
• Description: IC MON TIRE PRESS 433MHZ 24-SOIC
• Manufacturer: Atmel

Specifications of T48C862M-R4-TNQ

• Frequency: 433MHz
• Modulation Or Protocol: FM, FSK
• Data Rate - Maximum: 32 kBaud
• Power - Output: 10dBm
• Current - Transmitting: 9.5mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Memory Size: 1KB EEPROM, 1KB RAM
• Voltage - Supply: 2 V ~ 4 V
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 24-SOIC (0.200", 5.30mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Applications: -

Combination Mode 7:
Pulse-width Modulation
(PWM)
Combination Mode 8:
Manchester
Demodulation/Pulse-width
Demodulation
4551C–4BMCU–01/04
SSI mode 1:
Timer 3 mode 9: Pulse-width modulation with the shift register data (SO)
The two compare registers are used to generate two varied time intervals. The SSI data
output selects which compare register is used for the output pulse generation. In this
mode, both compare and compare mode registers must be programmed to generate the
two pulse width. It is also useful to enable the single-action mode for extreme duty
cycles. Timer 2 is used as baudrate generator and for the triggered restart of Timer 3.
The SSI must be supplied with the toggle signal of Timer 2. The counter is driven by an
internal or external clock source.
Figure 81. Pulse-width Modulation
SSI mode 1:
Timer 3 mode 10: Manchester demodulation/pulse-width demodulation with Timer 3
For Manchester demodulation, the edge detection stage must be programmed to detect
each edge at the input. These edges are evaluated by the demodulator stage. The timer
stage is used to generate the shift clock for the SSI. A compare register 1 match event
defines the correct moment for shifting the state from the input T3I as the decoded bit
into shift register. After that, the demodulator waits for the next edge to synchronize the
timer by a reset for the next bit. The compare register 2 can be used to detect a time
error and handle it with an interrupt routine.
Before activating the demodulator mode the timer and the demodulator stage must be
synchronized with the bitstream. The Manchester code timing consists of parts with the
half bitlength and the complete bitlength. A synchronization routine must start the
demodulator after an interval with the complete bitlength.
The counter can be driven by any internal clock source. The output T3O can be used by
Timer 2 in this mode. The Manchester decoder can also be used for pulse-width demod-
ulation. The input must programmed to detect the positive edge. The demodulator and
timer must be synchronized with the leading edge of the pulse. After that a counter
match with the compare register 1 shifts the state at the input T3I into the shift register.
The next positive edge at the input restarts the timer.
Counter 3
TOG2
CM31
CM32
SCO
T3R
T3O
SIR
SO
0 0 0 0 0 0 0 0 0
8-bit shift register internal data output (SO) to the Timer 3
8-bit shift register internal data input (SI) and the internal shift clock
(SCI) from the Timer 3
0
0 0 0 0
0
0 0 0 0 0 1 2 3 4 5 6 7 8 9 1011121314150 1 2 3 4 5
T48C862-R4 [Preliminary]
1
6 7 8
0
9
10
1112
13
14
15
0
1
2 3
1
4
83