T48C862M-R4-TNQ Atmel, T48C862M-R4-TNQ Datasheet - Page 41

• Manufacturer Part Number: T48C862M-R4-TNQ
• Description: IC MON TIRE PRESS 433MHZ 24-SOIC
• Manufacturer: Atmel

Specifications of T48C862M-R4-TNQ

• Frequency: 433MHz
• Modulation Or Protocol: FM, FSK
• Data Rate - Maximum: 32 kBaud
• Power - Output: 10dBm
• Current - Transmitting: 9.5mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Memory Size: 1KB EEPROM, 1KB RAM
• Voltage - Supply: 2 V ~ 4 V
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 24-SOIC (0.200", 5.30mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Applications: -

Figure 35. Timer 1 and Watchdog
4551C–4BMCU–01/04
CL1
T1C1 register
Write of the
T1C1
WDC
T1RM T1C2 T1C1 T1C0
WDL
WDR WDT1 WDT0
Decoder
Decoder
3
RES
CL
This timer starts running automatically after any power-on reset! If the watchdog func-
tion is not activated, the timer can be restarted by writing into the T1C1 register with
T1RM = 1.
Timer 1 can also be used as a watchdog timer to prevent a system from stalling. The
watchdog timer is a 3-bit counter that is supplied by a separate output of Timer 1. It gen-
erates a system reset when the 3-bit counter overflows. To avoid this, the 3-bit counter
must be reset before it overflows. The application software has to accomplish this by
reading the CWD register.
After power-on reset the watchdog must be activated by software in the $RESET initial-
ization routine. There are two watchdog modes, in one mode the watchdog can be
switched on and off by software, in the other mode the watchdog is active and locked.
This mode can only be stopped by carrying out a system reset.
The watchdog timer operation mode and the time interval for the watchdog reset can be
programmed via the watchdog control register (WDC).
Figure 34. Timer 1 Module
2
Q1 Q2 Q3 Q4
mode control
Watchdog
SUBCL
SYSCL
RES
Q5
MUX for watchdog timer
MUX for interval timer
Q6
MUX
T1CS
Q8
Q8
CL1
Q11
Q11
T48C862-R4 [Preliminary]
Prescaler
14 bit
T1MUX
Q14
Q14
T1C2
WDCL
T1MUX
SUBCL
WDCL
T1BP
T1BP T1IM
Divider / 8
Watchdog
T1IM
Watchdog
Divider
RESET
4 bit
CWD register
T1IM=0
T1IM=1
Read of the
INT2
T1OUT
RESET
(NRST)
NRST
INT2
T1OUT
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