HSP50216KIZ Intersil, HSP50216KIZ Datasheet - Page 8

• Manufacturer Part Number: HSP50216KIZ
• Description: IC DOWNCONVERTER DGTL 4CH 196BGA
• Manufacturer: Intersil

Specifications of HSP50216KIZ

• Function: Downconverter
• Rf Type: W-CDMA
• Package / Case: 196-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The parallel input busses are 16 bits wide. The input format
may be twos complement or offset binary format. A floating
point mode is also supported. The floating point modes and
the mapping of the parallel 16-bit input format is discussed
below.
Floating Point Input Mode Bit Mapping
The input bit weighting for fixed point inputs on busses A, B,
C, and D is:
Floating Point Input Mode Bit Mapping Tables
A(15:0), B(15:0), C(15:0) or D(15:0):
NOTES:
NOTE:
NOTE:
000
001
010
011
100
101 (Note 1)
000
001
010
011
100 (Note 3)
15
000
001
010
011 (Note 4)
1. Or 110 or 111, the exponent input saturates at 10.
2. “Xnn” = input A, B, C, or D bit nn.
3. Or 101, 110, or 111, the exponent input saturates at 100.
4. Or 100, 101, 110, or 111, the exponent input saturates at 011.
2
EXPONENT
EXPONENT
0
EXPONENT
14
2
-1
2
13
-2
0
6
12
18
24
30
0
6
12
18
24
0
6
12
18
GAIN (dB)
GAIN (dB)
GAIN (dB)
2
12
-3
12-BIT MODE: 12 to 13-BIT MANTISSA, 3-BIT EXPONENT, 24dB EXPONENT RANGE
11-BIT MODE: 11 to 13-BIT MANTISSA, 3-BIT EXPONENT, 30dB EXPONENT RANGE
2
11
13-BIT MODE: 13-BIT MANTISSA, 3-BIT EXPONENT, 18dB EXPONENT RANGE
-4
8
X15
X15
X15
X15
X15
X15
X15
X15
X15
X15
X15
X15
X15
X15
X15
2
10
-5
X15
X15
X15
X15
X15
X14
X15
X15
X15
X15
X14
2
X15
X15
X15
X14
9
-6
X15
X15
X15
X15
X14
X13
X15
X15
X15
X14
X13
2
X15
X14
X15
X13
8
-7
X15
X15
X15
X14
X13
X12
2
X15
X15
X14
X13
X12
X14
X13
7
X15
X12
-8
X15
X15
X14
X13
X12
X11
PIN BIT WEIGHTING TO 16-BIT INPUT MAPPING
PIN BIT WEIGHTING TO 16-BIT INPUT MAPPING
HSP50216
PIN BIT WEIGHTING TO 16-BIT INPUT MAPPING
2
X15
X14
X13
X12
X11
6
X14
X13
X12
-9
X11
X15
X14
X13
X12
X10
X11
2
X14
X13
X12
X11
X10
-10
X13
X12
X10
X11
5
X14
X13
X12
X10
X11
X9
bit 15 (MSB): 2
For floating point modes, the least significant 2 or 3 bits are
used as exponent bits (See Floating Point Input Mode Bit
Mapping Tables). The difference between the four floating
point modes with three exponent bits is where the exponent
saturates.
X13
X12
X10
X11
X9
X12
X10
2
X11
X13
X12
X10
X9
X11
-11
X9
X8
4
X12
X11
X10
X9
X8
X12
X10
X10
X11
X11
X9
X8
X7
X9
X8
2
-12
3
0
, bit 14: 2
X10
X11
X10
X11
X9
X8
X7
X9
X8
X7
X6
X10
X9
X8
X7
2
-13
X10
X10
X9
X8
X7
X6
X5
X9
X8
X7
X6
X8
X7
X9
X6
-1
/(exp2)
, bit 13: 2
2
X7
X6
X8
X5
X9
X8
X7
X6
X5
X9
X8
X7
X6
X5
X4
X5
X7
X6
X4
X8
X7
X6
X5
X4
-2
X8
X7
X6
X5
X4
X3
, ..., bit 0: 2
(exp1)
X6
X5
X4
X3
X7
X6
X5
X4
X3
1
X7
X6
X5
X4
X3
0
X5
X4
X3
X6
X5
X4
X3
0
0
August 17, 2007
-15
X6
X5
X4
X3
0
0
X4
X3
X5
X4
X3
(exp0)
0
0
0
0
.
FN4557.6
0
X5
X4
X3
X3
0
0
0
X4
X3
0
0
0
0
0
0