HSP50216KIZ Intersil, HSP50216KIZ Datasheet - Page 21

• Manufacturer Part Number: HSP50216KIZ
• Description: IC DOWNCONVERTER DGTL 4CH 196BGA
• Manufacturer: Intersil

Specifications of HSP50216KIZ

• Function: Downconverter
• Rf Type: W-CDMA
• Package / Case: 196-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Single FIR Basic Program
This is the basic program for a single FIR. This program applies to decimation filters (including DECx1) that are symmetric or
asymmetric (but not complex). The FIR output is routed through path A with the AGC enabled.
Wait Preload Register
This register (IWA register *00Ch) holds the wait counter
threshold and two wait counter decrement values. Each is
10 bits. The wait counter counts filter input samples until the
count is greater than or equal to the threshold. The wait
counter then asserts a flag to the filter compute engine.
The wait counter threshold is typically set to the total number
of input samples needed to generate a filter output. A “WAIT”
instruction in the filter compute engine waits for the wait
counter flag signal before proceeding. The filter compute
engine would then compute all the filters needed to produce
an output and then would jump back to the “WAIT”
instruction.
The wait counter is implemented with an accumulator. This
allows the count to go beyond the threshold without losing
the sample count. Two bits in the FIR instruction decrement
the wait counter (subtract a value) and select the decrement
value. The decrement value is typically the number of
samples needed for an output (total decimation), though it
0 - WAIT FOR ENOUGH SAMPLES
1 - FIR
2 - JUMP TO STEP 0
Four bit fields must be filled in:
The rest of the instruction RAM would typically be filled with NOP instructions:
00TT
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
F - filter type (this example applies to types 1-5)
D - decimation (also loaded into wait threshold)
T - number of taps minus 1
R - clocks/calculation (= floor((taps+1)/2) for symmetric, = taps for asymmetric)
TTTT
0000
0000
0000
0000
0001
1000
1011
0000
0000
0000
0000
0000
0000
0000
0000
TTTD
0000
0000
0000
0000
0101
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
21
DDDD
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
1111
DDDD
0FFF
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
1111
100R
FFF0
0000
0000
0000
0000
0000
1010
0000
0000
0000
0001
0000
0000
0000
0000
RRRR
HSP50216
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
1000
1100
RRRR
0000
0000
0000
0001
0000
1000
0000
0000
0000
0000
0000
0000
0000
0111
0111
can be a different value to ignore inputs and shift the timing.
(The read pointer increment must be adjusted as well.)
The filter compute engine sequencer does not count each
input sample or track whether each filter is ready to run.
Instead, the wait counter is used to determine whether there
are enough input samples to compute all the filters in the
chain and get an output sample from the entire filter chain.
This adds some additional delay since intermediate results
are not precalculated, but it simplifies the filter control. The
number of samples needed is equal to the total decimation
of the filter chain. For example, with two decimate-by-2
halfband filters and a decimate-by-2 shaping FIR, the total
decimation would be 8 so 8 samples are needed to compute
an output. HBF1 would compute four times to generate four
inputs to HBF2. HBF2 would compute twice to generate the
two samples that the shaping FIR needs to compute an
output.
127:96
127:96
127:96
127:96
95:64
64:32
95:64
63:32
95:64
64:32
95:64
64:32
31:0
31:0
31:0
31:0
08000A00h
00000000h
00000000h
00000000h
00000001h
00000000h
00000000h
00000000h
00000107h
00000000h
00000000h
00000000h
00000080h
0B00--C8h
015FF---h
-----007h
August 17, 2007
FN4557.6