HSP50216KIZ Intersil, HSP50216KIZ Datasheet - Page 40

• Manufacturer Part Number: HSP50216KIZ
• Description: IC DOWNCONVERTER DGTL 4CH 196BGA
• Manufacturer: Intersil

Specifications of HSP50216KIZ

• Function: Downconverter
• Rf Type: W-CDMA
• Package / Case: 196-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

P(31:0)
P(31:0)
P(15:0)
P(15:0)
P(15:0)
31:24
23:16
31:24
23:16
15:8
15:8
N/A
N/A
N/A
7:0
7:0
Fourth serial slot in Serial Data Output 2 (SD2x). x = A, B, C or D. See bits 7:0 of Table 24 for functional description of bits 23:16.
Third serial slot in Serial Data Output 2 (SD2x). x = A, B, C or D. See bits 7:0 of Table 24 for functional description of bits 23:16.
Second serial slot in Serial Data Output 2 (SD2x). x = A, B, C or D. See bits 7:0 of Table 24 for functional description of bits 15:8.
First serial slot in Serial Data Output 2 (SD2x). x = A, B, C or D. See bits 7:0 of Table 24 for functional description of bits 7:0.
Set to zero
Seventh serial slot in Serial Data Output 2 (SD2x). x = A, B, C or D. See bits 7:0 of Table 24 for functional description of bits 23:16.
Sixth serial slot in Serial Data Output 2 (SD2x). x = A, B, C or D. See bits 7:0 of Table 24 for functional description of bits 15:8.
Fifth serial slot in Serial Data Output 2 (SD2x). x = A, B, C or D. See bits 7:0 of Table 24 for functional description of bits 7:0.
Writing to this location resets the following activities of the functional block indicated.
Writing to this location inserts one extra data sample in the CIC to FIR path by repeating a sample. Used for shifting the FIR filter
compute engine timing.
Writing to this location deletes one data sample in the CIC to FIR path. Used for shifting the FIR filter compute engine timing.
Input Format/Select, NCO, Mixer and CIC.
Filter Compute Engine:
AGC:
Cartesian-to-Polar Coordinate Converter:
FIFO:
Resampler Timing NCO:
Output Section:
Self Test Control:
Clears any pending enable in each channel's input demultiplexer function, loads the CIC decimation counter (the load value
is indeterminate if the decimation counter preload register has not been loaded), clears all processing enables (stops all
processing in the data path, but does not clear the data path registers).
Resets the Read/Write pointers, fetch instruction 31 and start the filter program execution.
Resets the compute blocks in both the forward and loop filter blocks (any calculations in progress are lost).
Resets the compute blocks (any calculations in progress are lost).
Resets counter (clears the FIFO, all data is lost).
Clears the slave (active) frequency registers and clears the phase accumulator.
Resets the serial output section (clears all registers, counters, and flags but does not clear the configuration registers).
Resets the self test control logic of the front end (Input Format/Select, NCO, Mixer, and CIC) and the back end (Filter Compute
Engine, AGC, and Cartesian-to-Polar Coordinate Converter).
TABLE 26. SERIAL DATA OUTPUT 2 CONTENT/FORMAT REGISTER 1 (IWA = *017h)
TABLE 27. SERIAL DATA OUTPUT 2 CONTENT/FORMAT REGISTER 2 (IWA = *018h)
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TABLE 29. CHANNEL TIMING ADVANCE STROBE REGISTER (IWA = *01Ah)
TABLE 30. CHANNEL TIMING RETARD STROBE Register (IWA = *01Bh)
TABLE 28. SOFTWARE RESET REGISTER (IWA = *019h)
HSP50216
FUNCTION
FUNCTION
FUNCTION
FUNCTION
FUNCTION
August 17, 2007
FN4557.6