TWR-56F8257 Freescale Semiconductor, TWR-56F8257 Datasheet - Page 72

• Manufacturer Part Number: TWR-56F8257
• Description: TOWER SYSTEM KIT MC56F8257
• Manufacturer: Freescale Semiconductor
• Type: DSC, Digital Signal Controllerr

Specifications of TWR-56F8257

• Contents: Board, Cables, Documentation, DVD
• For Use With/related Products: Freescale Tower System, MC56F8257
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Design Considerations
B, the internal [state-dependent] component, reflects the supply current required by certain on-chip resources only when those
resources are in use. These resources include RAM, flash memory, and the ADCs.
C, the internal [dynamic] component, is classic C*V
standard cell logic.
D, the external [dynamic] component, reflects power dissipated on-chip as a result of capacitive loading on the external pins of
the chip. This component is also commonly described as C*V
56800E reveal that the power-versus-load curve does have a non-zero Y-intercept.
E, the external [static] component, reflects the effects of placing resistive loads on the outputs of the device. Total all V
IV to arrive at the resistive load contribution to power. Assume V = 0.5 for the purposes of these rough calculations. For
instance, if there is a total of nine PWM outputs driving 10 mA into LEDs, then P = 8*0.5*0.01 = 40 mW.
In previous discussions, power consumption due to parasites associated with pure input pins is ignored and assumed to be
negligible.
8
8.1
An estimation of the chip junction temperature, T
where:
The junction-to-ambient thermal resistance is an industry-standard value that provides a quick and easy estimation of thermal
performance. Unfortunately, there are two values in common usage: the value determined on a single-layer board and the value
obtained on a board with two planes. For packages such as the PBGA, these values can be different by a factor of two. Which
72
Power due to capacitive loading on output pins is (first order) a function of the capacitive load and frequency at which
the outputs change.
capacitive load. In these cases,
where:
— Summation is performed over all output pins with capacitive loads.
— Total power is expressed in mW.
— C
Because of the low duty cycle on most device pins, power dissipation due to capacitive loads was found to be fairly
low when averaged over a period of time.
Design Considerations
Thermal Design Considerations
load
is expressed in pF.
TotalPower = ((Intercept + Slope*C
Table 45
MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
R
P
T
Table 45. I/O Loading Coefficients at 10 MHz
A
J
D
provides coefficients for calculating power dissipated in the I/O cells as a function of
8 mA drive
4 mA drive
Equation 2
= Ambient temperature for the package (
= Junction-to-ambient thermal resistance (
= Power dissipation in the package (W)
T
J
J
, can be obtained from
= T
applies.
2
*F CMOS power dissipation corresponding to the 56800E core and
A
+ (R
2
*F, although simulations on two of the I/O cell types used on the
J
Intercept
1.15 mW
x P
load
1.3
D
)*frequency/10 MHz)
)
Equation
0.11 mW/pF
0.11 mW/pF
3.
Slope
o
C)
o
C/W)
Freescale Semiconductor
Eqn. 2
Eqn. 3
2
/R or