TWR-56F8257 Freescale Semiconductor, TWR-56F8257 Datasheet - Page 4

• Manufacturer Part Number: TWR-56F8257
• Description: TOWER SYSTEM KIT MC56F8257
• Manufacturer: Freescale Semiconductor
• Type: DSC, Digital Signal Controllerr

Specifications of TWR-56F8257

• Contents: Board, Cables, Documentation, DVD
• For Use With/related Products: Freescale Tower System, MC56F8257
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Overview
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Efficient 56800E digital signal processor (DSP) engine with modified Harvard architecture
— Three internal address buses
— Four internal data buses
As many as 60 million instructions per second (MIPS) at 60 MHz core frequency
155 basic instructions in conjunction with up to 20 address modes
32-bit internal primary data buses supporting 8-bit, 16-bit, and 32-bit data movement, addition, subtraction, and logical
operation
Single-cycle 16
Four 36-bit accumulators, including extension bits
32-bit arithmetic and logic multi-bit shifter
Parallel instruction set with unique DSP addressing modes
Hardware DO and REP loops
Instruction set supports DSP and controller functions
Controller-style addressing modes and instructions for compact code
Efficient C compiler and local variable support
Software subroutine and interrupt stack with depth limited only by memory
JTAG/enhanced on-chip emulation (EOnCE) for unobtrusive, processor speed–independent, real-time debugging
3.0 V to 3.6 V operation (power supplies and I/O)
From power-on-reset: approximately 2.7 V to 3.6 V
Ambient temperature operating range: –40 °C to +105 °C
Dual Harvard architecture that permits as many as three simultaneous accesses to program and data memory
48 KB (24K x 16) to 64 KB (32K x 16) on-chip flash memory with 2048 bytes (1024 x 16) page size
6 KB (3K x 16) to 8 KB (4K x 16) on-chip RAM with byte addressable
EEPROM emulation capability using flash
Support for 60 MHz program execution from both internal flash and RAM memories
Flash security and protection that prevent unauthorized users from gaining access to the internal flash
Five interrupt priority levels
— Three user programmable priority levels for each interrupt source: Level 0, 1, 2
— Unmaskable level 3 interrupts include: illegal instruction, hardware stack overflow, misaligned data access, and
— Maskable level 3 interrupts include: EOnCE step counter, EOnCE breakpoint unit, and EOnCE trace buffer
Overview
MC56F825x/MC56F824x Features
SWI3 instruction
Core
Operation Range
Memory
Interrupt Controller
16-bit parallel multiplier-accumulator (MAC)
MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
Freescale Semiconductor