TWR-56F8257 Freescale Semiconductor, TWR-56F8257 Datasheet - Page 60

• Manufacturer Part Number: TWR-56F8257
• Description: TOWER SYSTEM KIT MC56F8257
• Manufacturer: Freescale Semiconductor
• Type: DSC, Digital Signal Controllerr

Specifications of TWR-56F8257

• Contents: Board, Cables, Documentation, DVD
• For Use With/related Products: Freescale Tower System, MC56F8257
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Specifications
7.17
7.18
60
1
2
3
Delay from Interrupt Assertion to Fetch of first
In the formulas, T = system clock cycle and T
At 4 MHz (used coming out of reset and stop modes), T = 250 ns.
Parameters listed are guaranteed by design.
This minimum number guarantees that a reliable reset occurs.
RESET deassertion to First Address Fetch
Minimum GPIO pin Assertion for Interrupt
Minimum RESET Assertion Duration
GPIO pin
(Input)
Reset, Stop, Wait, Mode Select, and Interrupt Timing
Queued Serial Peripheral Interface (SPI) Timing
instruction (exiting Stop)
Characteristic
Clock (SCK) high time
Clock (SCK) low time
Enable lead time
Enable lag time
Characteristic
Table 33. Reset, Stop, Wait, Mode Select, and Interrupt Timing
Cycle time
Master
Master
Master
Master
Master
Figure 19. GPIO Interrupt Timing (Negative Edge-Sensitive)
Slave
Slave
Slave
Slave
Slave
MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
All address and data buses described here are internal.
3
osc
= oscillator clock cycle. For an operating frequency of 32 MHz, T = 31.25 ns.
Table 34. SPI Timing
Symbol
t
t
t
RDA
t
RA
IW
IF
t
IW
NOTE
Symbol
96T
Typical Min
t
t
ELG
t
ELD
t
t
CH
CL
C
OSC
4T
2T
—
+ 64T
1
62.5
Min
125
125
31
50
31
50
31
—
—
97T
Typical Max
OSC
6T
—
—
Max
—
—
—
—
—
—
—
—
—
—
+ 65T
1,2
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Freescale Semiconductor
Unit
ns
ns
ns
ns
See Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure 23
Figure 23
Figure 23
Figure 23
Figure 23
Refer to
Figure 19
—
—
—
20,
21,
22,
20,
21,
22,